32
Am79Q02/021/031 Data Sheet
7. Transmit time slots and receive time slots are set to
0, 1, 2 , a nd 3 for ch an ne ls 1, 2, 3, an d 4,
respectively. The clock slots are set to 0, with
transmit on the negative edge.
8. DXA port is selected for all channels.
9. DRA port is selected for all channels.
10. The master clock frequency selected is 8.192 MHz
and is programmed to come from PCLK.
11. All four channels are selected in the Channel
Enable register.
12. Any pending interrupts are cleared, all interrupts
are masked, and the Interrupt Output state is set to
open drain.
13. The supervision debounce time is set to 8 ms.
14. The previously programmed B, Z, X, R, GX, and
GR filters are unchanged.
15. The chopper clock frequency is set to 256 kHz but
the chopper clock is turned off.
16. The E1 Multiplex state is turned off and the polarity
is set for high going pulses.
17. No signalling on the PCM highway.
SIGNAL PROCESSING
Overview of Digital Filters
Several of the blocks in the signal processing section
are user programmable. These allow the user to
optimize the performance of the QSLAC device for the
system. Figure 12 shows the QSLAC device signal
processing and indicates the programmable blocks.
The advantages of digital filters are:
High reliability
No drift with time or temperature
Unit-to-unit repeatability
Superior transmission performance
Flexibility
Maximum possible bandwidth for V.34 modems
TSA
AR
AISN
Cutoff
Transmit
Path
(CTP)
Lower Receive
Gain (RG)
Full
Digital
Loop
back
(FDL)
GX
AX
TSA
Loopback
(TLB)
R
GR
X
ADC
Deci-
mator
DAC
LPF
& HPF
Com-
pressor
Ex-
pander
LPF
VOUT
VIN
TSA
B
Inter-
polator
Figure 12. QSLAC Device Block Diagram
+
+
+
Z
Digital
TX
Digital
RX
Inter-
polator
Deci-
mator
21108-027
High Pass Filter (HPF)
0
1 kHz Tone
(TON)
Cutoff Receive
Path (CRP)
VREF
*
*
*
*
*
*
*
*
*
* programmable blocks
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