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Am79Q02/021/031 Data Sheet
Figure 9. SLIC I/O, E1 Multiplex and Real-Time Data Register Operation
—— CD1B C5
C4
C3 CD2 CD1
DQ
EN/HOLD
CD1
CD2
C3
C4
C5
DQ
EN/HOLD
0
1
Output Latch
I/O Direction
MPI Command 22
Register
EE1 Bit
SLIC Output
Data Register
MPI Command 20
SLIC I/O Register
MPI Command 20,
21
LD Enable
*
Delay
GK Enable
*
E1 Source
E1P
MCLK/E1
MUX
CDB1 CDA1
Real Time
Data Register
(Command 16, 17)
Interrupt Mask
Register
(Command 26, 27)
(Channel 1
Shown)
{Samefor
Channels
2, 3, 4
(CMD 28, 29, Bit 3)
ATI
Ground Key Filter
(time set via
Commands 52, 53)
MCDB1 MCDA1
Debounce
(time set via
Commands 45, 46)
INT
Note:
* Transparent latches: When enable input is high, Q output follows D input. When enable input
goes low, Q output is latched at last state.
(Internal)
See Figure 10
for details
CDA4
CDA3
CDA2
CDB4
CDB3
CDB2
MCDB4 MCDA4 MCDB3 MCDA3 MCDB2 MCDA2
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