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Am79Q02/021/031 Data Sheet
Figure 11. MPI Real-Time Data Register or GCI Upstream SC Channel Data
1 kHz
UP/DN
GK=0
Six-State
Up/Down
GK
GK=0
Counter
*
a. Loop Detect Debounce Filter
8
DQ
DQ
DQ
RST
D
Q
EN/HOLD
FS
(8 kHz)
CD1
CDA
CK
DSH0–DSH3
Debounce Period
(0–15 ms)
Q
Debounce Counter
* Transparent latch: Output follows input when EN is high; output holds last state when EN is low
Debounce Counter: Output goes high after counting to programmed (DSH) number of 1 ms clocks;
Counter is reset for CD1 input changes at 125
µs sample period.
DSH0–DSH3 programmed value is common for all 4 channels, but debounce counter is separate per channel
Notes:
RST
GK0–GK3
Ground-Key
(1–15 ms)
Sampling Interval
Q
CD2 or CD1B
CDB
MUX
Clock Divider
(1–15 ms
clock output)
b. Ground-Key Filter
Programmed value of GK0–GK3 determines clock rate (1–15 ms) of six-state counter.
Notes:
If GK value = 0, counter is bypassed and no buffering occurs.
Six-state up/down counter: Counts up when input is high; counts down when input is low.
Output goes and stays high when maximum count is reached;
output goes and stays low when counts down to zero.
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