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SLAC Products
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10, 11. Write/Read Transmit Clock Slot, Receive Clock Slot, and Transmit Clock Edge
MPI Command
(44/45h)
R/W = 0: Write
R/W = 1: Read
Transmit on A and B
TAB = 0*
Transmit data on highway selected by TPCM (See Commands 6,7
on page 40).
TAB = 1
Transmit data on both highways A and B
Transmit Edge
XE = 0*
Transmit changes on negative edge of PCLK
XE = 1
Transmit changes on positive edge of PCLK
Receive Clock Slot
RCS = 0*–7
Receive Clock Slot number
Transmit Clock Slot
TCS = 0*–7
Transmit Clock Slot number
The XE bit and the clock slots apply to all four channels; however, they cannot be written or read
unless at least one channel is selected in the Channel Enable Register.
* Power Up and Hardware Reset (RST) Value = 00h.
12, 13. Write/Read Configuration Register
MPI Command
(46/47h)
R/W = 0: Write
R/W = 1: Read
Interrupt Mode
INTM = 0
TTL-compatible output
INTM = 1*
Open drain output
Chopper Clock Control
CHP = 0*
Chopper Clock is 256 kHz (2048/8 kHz)
CHP = 1
Chopper Clock is 292.57 kHz (2048/7 kHz)
PCM Signaling Mode
SMODE = 0*
No signaling on PCM highway
SMODE = 1
Signaling on PCM highway
Clock Source Mode
CMODE = 0
MCLK used as master clock; no E1 multiplexing allowed
CMODE = 1*
PCLK used as master clock; E1 multiplexing allowed if enabled in
commands 49, 50.
The master clock frequency can be selected by CSEL. The master clock frequency selection
affects all channels.
D7
D6
D5
D4
D3
D2
D1
D0
Command
0
1
0
0
0
1
0
R/W
I/O Data
TAB
XE
RCS2
RCS1
RCS0
TCS2
TCS1
TCS0
D7
D6
D5
D4
D3
D2
D1
D0
Command
0
1
0
0
0
1
1
R/W
I/O Data
INTM
CHP
SMODE
CMODE
CSEL3
CSEL2
CSEL1
CSEL0
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