44
Am79Q02/021/031 Data Sheet
20, 21. Write/Read SLIC Input/Output Register
MPI Command
(52/53h)
R/W = 0: Write
R/W = 1: Read
RSVD
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
Pins CD1, CD2, and C3 through C5 are set to 1 or 0. The data appears latched on the CD1,
CD2, and C3 through C5 SLIC I/O pins, provided they were set in the Output mode (see
Command 22). The data sent to any of the pins set to the Input mode is latched, but does not
appear at the pins. The CD1B bit is only valid if the E1 Multiplex mode is enabled (EE1 = 1).
* Power Up and Hardware Reset (RST) Value = 00h
22, 23. Write/Read SLIC Input/Output Direction, Read Status Bits
MPI Command
(54/55h)
RSVD
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
Channel Status (Read status only, write as 0)
CSTAT = 0
Channel is inactive (Standby mode).
CSTAT = 1
Channel is active.
Clock Fail (Read status only, write as 0)
CFAIL* = 0
The internal clock is synchronized to frame synch.
CFAIL = 1
The internal clock is not synchronized to frame synch.
* The CFAIL bit is independent of the Channel Enable Register.
I/O Direction (Read/Write)
IOD5 = 0*
C5 is an input
IOD5 = 1
C5 is an output
IOD4 = 0*
C4 is an input
IOD4 = 1
C4 is an output
IOD3 = 0*
C3 is an input
IOD3 = 1
C3 is an output
IOD2 = 0*
CD2 is an input
IOD2 = 1
CD2 is an output
IOD1 = 0*
CD1 is an input
IOD1 = 1
CD1 is an output
Pins CD1, CD2, and C3 through C5 are set to Input or Output modes individually. Pins C3–C5
are not available on the Am79Q031 QSLAC device, and C5 is available only on the Am79Q021
QSLAC device.
* Power Up and Hardware Reset (RST) Value = 00h
D7
D6
D5
D4
D3
D2
D1
D0
Command
0
1
0
1
0
0
1
R/W
I/O Data
RSVD
RSVD
CD1B
C5
C4
C3
CD2
CD1
D7
D6
D5
D4
D3
D2
D1
D0
Command
0
1
0
1
0
1
0
R/W
Input Data
RSVD
CSTAT
CFAIL
IOD5
IOD4
IOD3
IOD2
IOD1
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