M50FLW080A datasheet(22/64 Pages) STMICROELECTRONICS

номер детали	M50FLW080A

подробное описание детали	8 Mbit (13 x 64KByte Blocks 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory

PDF	64 Pages

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производитель	STMICROELECTRONICS [STMicroelectronics]

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Bus operations

M50FLW080A, M50FLW080B

22/64

Figure 8.

LPC Bus Read waveforms (1-byte)

Table 8.

LPC Bus Read field definitions (1-byte)

Clock

Cycle

Number

Clock

Cycle

Count

Field

LAD0-

LAD3

Memory

I/O

Description

START

0000b

On the rising edge of CLK with LFRAME Low,

the contents of LAD0-LAD3 must be 0000b to

indicate the start of a LPC cycle.

CYCTYPE

+ DIR

0100b

Indicates the type of cycle and selects 1-byte

reading. Bits 3:2 must be 01b. Bit 1 indicates

the direction of transfer: 0b for read. Bit 0 is

Don’t Care.

3-10

ADDR

XXXX

A 32-bit address is transferred, with the most

significant nibble first. A23-A31 must be set

to 1. A22=1 for memory access, and A22=0

for register access. Table 5 shows the

appropriate values for A21-A20.

TAR

1111b

The host drives LAD0-LAD3 to 1111b to

indicate a turnaround cycle.

TAR

1111b

(float)

The LPC Flash Memory takes control of

LAD0-LAD3 during this cycle.

13-14

WSYNC

0101b

The LPC Flash Memory drives LAD0-LAD3

to 0101b (short wait-sync) for two clock

cycles, indicating that the data is not yet

available. Two wait-states are always

included.

RSYNC

0000b

The LPC Flash Memory drives LAD0-LAD3

to 0000b, indicating that data will be available

during the next clock cycle.

16-17

DATA

XXXX

Data transfer is two CLK cycles, starting with

the least significant nibble.

TAR

1111b

The LPC Flash Memory drives LAD0-LAD3

to 1111b to indicate a turnaround cycle.

TAR

1111b

(float)

N/A

The LPC Flash Memory floats its outputs, the

host takes control of LAD0-LAD3.

AI04429

CLK

LFRAME

LAD0-LAD3

Number of

clock cycles

START

CYCTYPE

+ DIR

ADDR

TAR

SYNC

DATA

TAR

1182322

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