M50FLW080A datasheet(14/64 Pages) STMICROELECTRONICS

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Signal descriptions

M50FLW080A, M50FLW080B

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2.1.4

General-purpose inputs (GPI0-GPI4)

The General Purpose Inputs can be used as digital inputs for the CPU to read, with their

contents being available in the General Purpose Inputs Register. The pins must have stable

data throughout the entire cycle that reads the General Purpose Input Register. These pins

should be driven Low, VIL, or High, VIH, and must not be left floating.

2.1.5

Interface configuration (IC)

The Interface Configuration input selects whether the FWH/LPC interface or the

Address/Address Multiplexed (A/A Mux) Interface is used. The state of the Interface

Configuration, IC, should not be changed during operation of the memory device, except for

selecting the desired interface in the period before power-up or during a Reset.

To select the FWH/LPC Interface, the Interface Configuration pin should be left to float or

driven Low, VIL. To select the Address/Address Multiplexed (A/A Mux) Interface, the pin

should be driven High, VIH. An internal pull-down resistor is included with a value of RIL;

there will be a leakage current of ILI2 through each pin when pulled to VIH.

2.1.6

Interface Reset (RP)

The Interface Reset (RP) input is used to reset the device. When Interface Reset (RP) is

driven Low, VIL, the memory is in Reset mode (the outputs go to high impedance, and the

current consumption is minimized). When RP is driven High, VIH, the device is in normal

operation. After exiting Reset mode, the memory enters Read mode.

2.1.7

CPU Reset (INIT)

The CPU Reset, INIT, signal is used to Reset the device when the CPU is reset. It behaves

identically to Interface Reset, RP, and the internal Reset line is the logical OR (electrical

AND) of RP and INIT.

2.1.8

Clock (CLK)

The Clock, CLK, input is used to clock the signals in and out of the Input/Output

Communication Pins, FWH0/LAD0-FWH3/LAD3. The Clock conforms to the PCI

specification.

2.1.9

Top Block Lock (TBL)

The Top Block Lock input is used to prevent the Top Block (Block 15) from being changed.

When Top Block Lock, TBL, is driven Low, VIL, program and erase operations in the Top

Block have no effect, regardless of the state of the Lock Register. When Top Block Lock,

TBL, is driven High, VIH, the protection of the Block is determined by the Lock Registers.

The state of Top Block Lock, TBL, does not affect the protection of the Main Blocks (Blocks

0 to 14). For details, see Appendix A.

Top Block Lock, TBL, must be set prior to a program or erase operation being initiated, and

must not be changed until the operation has completed, otherwise unpredictable results

may occur. Similarly, unpredictable behavior is possible if WP is changed during Program or

Erase Suspend, and care should be taken to avoid this.

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