SCD1283 datasheet(63/94 Pages) INTEL

63 / 94 page

IEEE 1284-Compatible Parallel Interface — CD1283

Datasheet

7.3.9

Parallel FIFO Empty Pointer Register

This register contains the internal empty location pointer of the FIFO. It identifies the location in

the FIFO from which the next byte of data will transfer from the FIFO.

The PFEP register is cleared by a device or FIFO reset.

7.3.10

Parallel FIFO Fill Pointer Register

This register holds the internal fill location pointer of the FIFO. It identifies the location in the

FIFO to receive the next data byte from the pipeline.

The PFFP register is cleared by a device or FIFO reset.

7.3.11

Parallel FIFO Holding Registers

Set Tag: This bit specifies that the next character written to the parallel channel through the PFHR1 is to be tagged

as an ECP or EPP special character. This bit is cleared by the write to PFHR1, thus this bit must be set each time a

tagged character is to be written.

Error Interrupt Enable: This bit enables a non-zero DataErr status to cause an interrupt (if IntEn is also set).

DMA Buffer Write Enable: This bit must be set to enable host writes to the DMABUF register. It also enables the

FIFO data pipeline to empty DMABUF when it has been written to by the host system. In this case, the system will

write to the DMA buffer and not use DMA transfers, providing a low-performance alternative to DMA transfers.

Bit

Description (Continued) (Sheet 2 of 2)

Access: R/W

8-Bit Hex Address: 39

Default Value: 00

Bit 7

Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

6-Bit Binary FIFO Pointer Value

Access: R/W

8-Bit Hex Address: 38

Default Value: 00

Bit 7

Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

6-Bit Binary FIFO Pointer Value

Access: R/W

8-Bit Hex Address: 35

Default Value: 00

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

8-Bit Character Data

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