SCD1283 datasheet(71/94 Pages) INTEL

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IEEE 1284-Compatible Parallel Interface — CD1283

Datasheet

7.4.8

Parallel Channel Interrupt Enable Register

7.4.9

Parallel Channel Interrupt Status Register

The PCIER and PCISR provide control and status of interrupts generated by the parallel channel

control state machine. They have the same bit definitions. Each bit in the PCIER enables the

interrupt of the same type in the PCISR. A write of any value to the PCISR in response to an

interrupt request, causes it to clear and the interrupt request to be removed.

7.4.10

Parallel Configuration Register

Access: R/W

8-Bit Hex Address: 22

Default Value: 00

Bit 7

Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

TimEn

NegCh

SigCh

EPPAW

DirCh

IDReq

nINIT

Access: R/W

8-Bit Hex Address: 23

Default Value: 00

Bit 7

Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

TimOvr

NegCh

SigCh

EPPAW

DirCh

IDReq

nINIT

Bit

Description

Reserved: This read-only bit is always ‘0’.

TimEn/TimOvr: Used for factory test purposes only.

NegCh: The state of this bit indicates that a change occurred in the negotiation status of the port. The NSR

indicates the new status of the parallel port.

SigCh: This bit instructs the parallel port to generate an interrupt when any of the signals specified by the

ZDR or ODR change state as programmed.

EPPAW: The state of this bit indicates that the remote master has written an EPP address to the CD1283.

The new EPP address value is placed in the EAR.

DirCh: This bit indicates that the host-side parallel port changed the direction of the interface. Generally, this

is in response to a request made by the CD1283 through the RevRq bit in the SCR (bit 0). DirCh indicates that

the direction was reversed through the defined protocol and the CD1283 can now send data to the master.

This bit is only valid in ECP and EPP (bidirectional) modes.

IDReq: The state of this bit indicates that the host has requested that the CD1283 send its ID data string. The

peripheral host should send the appropriate ID string (this is application-dependent).

nINIT: This interrupt is generated when an nINIT pulse is received in Compatibility mode. The interrupt occurs

on the leading edge of the nINIT pulse.

Access: R/W

8-Bit Hex Address: 20

Default Value: 00

Bit 7

Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

ManMd

E1284

ETxfr

Ig_SEL

HTmrTst[1]

HTmrTst[0]

MMDir

ManOE

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