SCD1283 datasheet(29/94 Pages) INTEL

29 / 94 page

IEEE 1284-Compatible Parallel Interface — CD1283

Datasheet

Figure 5. Interrupt Generation Logic (Continued)

A1284 signal transition

from low-to-high, and

A1284(ODR[3]) = 1

nInit signal transition

from low-to-high, and

nInit(ODR[2]) = 1

HstBsy signal transition

from low-to-high, and

HstBsy(ODR[1]) = 1

HstClk signal transition

from low-to-high, and

HstClk(ODR[0]) = 1

ManMd

(PCR[7])

SigCh

(PCIER[4])

SigCh

(PCISR[4])

NOTE: Interface must be in Compatibility mode when

ManMd (PCR[7]) is set or ManMd has no affect

HstClk signal transition

from high-to-low, and

HstClk(ZDR[0]) = 1

HstBsy signal transi-

tion from high-to-low,

and

HstBsy(ZDR[1]) = 1

A1284 signal transi-

tion from high-to-low,

and

A1284(ZDR[3]) = 1

nInit signal transition

from high to low, and

nInit(ZDR[2]) = 1

Host has reversed the direction of the interface from ECP-forward to

ECP-reverse by driving nReverseRequest (nInit) signal low.

Host has changed the direction of the interface from ECP-reverse to ECP-

forward by driving nReverseRequest (nInit) signal high.

DirCh

(PCISR[2])

EPPAW

(PCISR[3])

nInit

(PCISR[0])

EPPAW

(PCIER[3])

EPP address received

on parallel port

nInit

(PCIER[0])

In Compatibility mode, the host

has requested the peripheral to

re-initialize itself (nInit went

low).

INTEN

(PFCR[4])

PPort

(PIR[6])

(PCISR[5])

NegCh

(PCISR[4])

SigCh

(PCISR[3])

EPPAW

(PCISR[2])

DirCh

(PCISR[1])

IDReq

(PCISR[0])

nInit

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