SCD1283 datasheet(49/94 Pages) INTEL

49 / 94 page

IEEE 1284-Compatible Parallel Interface — CD1283

Datasheet

The following section of programming code shows a typical initialization sequence preparing the

parallel channel for Compatibility mode data reception and enabling negotiation into all modes,

except EPP. This procedure can also be used as part of a diagnostic test suite. The device will

complete internal initialization within 500

µsec. Therefore, a timer (software or hardware) can be

used to detect that the operation does not complete within this time and that the device may not be

functional.

/* Initialization of the parallel channel consists of setting the SPR, selecting

modes that will be supported during negotiation, stale data timeout value,

initalizing the FIFO, the source for interrupts that will be accepted and other

operational functions. */

par_init()

{

/* First, issue chip reset command */

outportb(GFRCR, 0x00);

/* Clear the GFRCR */

outportb(AER, 0x02);

/* AER must equal 02h or o3h to access RCR*/

while (inportb(RCR) != 0x00)

;

/* Wait for RCR to clear */

outportb(RCR, 0x81);

while (inportb(GFRCR) != 0x00);/* Wait for GFRCR to be cleaared */

while (inportb(GFRCR) != 0x25);/* Wait for GFRCR to be set */

/* Start by initializing the parallel channel */

outportb(AER, 0x00);

/* Set the Access Enable Register */

outportb(SPR, 0x0d);

/* Assume 25MHz clock, set short pulse value */

outportb(NER, 0x4f);

/* Support all modes except EPP */

outportb(OVR, 0x18);

/* Start in Compatibility mode, set status

signals: */

PError = 0 */

/* SELCT = 1 */

/* nFault = 1 */

outportb(PCIER, 0x37);

/* Enable all interrupts except EPP Address

Write */

outportb(PCR, 0x60);

/* Enable 1284 negotiations and transfers */

/* Next, set up the pipeline control registers */

outportb(LIVR, 0x00);

/* Initialize the interrupt vector to 0 */

outportb(PFCR, 0xd8);

/* Enable pipeline DMA, set the direction to

input, */

/* enable interrupts (but not error ints) and

reset*/

/* the FIFO. At reset, it is assumed that the

starting */

/* direction will be input. */

outportb(PFCR, 0x58);

/* Remove Reset */

outportb(PFTR, 0x20);

/* Set the DMA threshold for receive (burst =

32) */

outportb(SDTPR, 0x64);

/* Set the stale data timeout period to 10ms */

outportb(PACR, 0x02);

/* Set asynchronous DMA mode */

}

6.2.2

Service Acknowledge Handling

Service request and acknowledge processing, as well as DMA request and acknowledge

processing, is performed by the internal MPU. It is important to take the behavior of the MPU into

account if interrupts are used. There are two different variations where service requests can be

serviced. One variation uses the SVCACKP*, the other does not. If the SVCACKP* signal is

activated through an input instruction then the device will return the value of the LIVR on the data

bus. This can be used as a vector to the service routine or used in a switch instruction to jump to the

correct routine.

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