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SCD1283 датащи(PDF) 23 Page - Intel Corporation |
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SCD1283 датащи(HTML) 23 Page - Intel Corporation |
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23 / 94 page ![]() IEEE 1284-Compatible Parallel Interface — CD1283 Datasheet 23 The CD1283 is a synchronous device. All internal operations occur on edges and levels (phases) of the internal clock. The internal clock is generated by dividing the external (system) clock by two. When the CPU performs an I/O cycle with the CD1283, it strobes; address and data are sampled on the rising edges of the internal clock. As illustrated in Chapter 8.0, external control signals must meet setup times with respect to system clock edges. Once a cycle starts, the sequence of events is locked to the CD1283 clock, with events (address setup, write data setup, and read data available) occurring at predictable times. It is not necessary to design a synchronous interface to the CD1283. In an asynchronous design, the DTACK* (Data Transfer Acknowledge) signal indicates that the CD1283 has completed the requested data transfer for all I/O cycles except DMA. DTACK* can be an input to wait-state generation logic that pauses the CPU until the operation is complete. If the CS* and DS* strobes (Chip Select and Data Strobe) do not meet the minimum setup time with respect to the system clock edge, the CD1283 does not detect the I/O request, and the cycle delays for two full-system clock cycles, meeting the setup time. The I/O cycle commences and follows the predictable timing with DTACK* signaling the end. Figure 2. Functional Block Diagram Figure 3. Internal Address Generation BUS INTERFACE AND DMA LOGIC PARALLEL PORT FIFO PARALLEL PORT LOGIC CONTROL STATE MACHINE INTERRUPT LOGIC REGISTERS PIPELINE PIPELINE CONTROL CPU ADDRESS ADDRESS GENERATION AER RAM REGISTER ARRAY PARALLEL PORT REGISTERS |
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