AD9119BBCZ datasheet(65/66 Pages) AD

65 / 66 page

Data Sheet

AD9119/AD9129

Rev. B | Page 65 of 66

Table 59. Bit Descriptions for Parity Err Falling

Bits

Bit Name

Description

Reset

Access

[7:0]

Parity falling edge error count

Number of falling edge-based errors detected, clipped to 256

0x00

Delay Control Register 0

Address: 0x70, Reset: 0xFF, Name: Delay Ctrl 0

Table 60. Bit Descriptions for Delay Ctrl 0

Bits

Bit Name

Description

Reset

Access

[7:0]

Enable delay cell

Sets each bit to enable or disable the delay cell, Bits[7:0]; delay cell number corresponds to bit

number

1: enables delay cell (default)

0: disables delay cell

0xFF

R/W

Delay Control Register 1

Address: 0x71, Reset: 0x67, Name: Delay Ctrl 1

Table 61. Bit Descriptions for Delay Ctrl 1

Bits

Bit Name

Description

Reset

Access

[7:3]

Reserved

0x60

R/W

[2:0]

Enable delay cell

Sets each bit to enable or disable the delay cell, Bits[10:8]; delay cell numbers are 10, 9,

and 8, which correspond to Bit 2, Bit 1, and Bit 0, respectively

1: enables delay cell (default)

0: disables delay cell

0x7

R/W

Drive Strength Register

Address: 0x7C, Reset: 0x7C, Name: Drive Strength

Table 62. Bit Descriptions for Drive Strength

Bits

Bit Name

Description

Reset

Access

[7:6]

DCO drive strength

Sets DCO drive strength

00: 2 mA

01: 2.8 mA (default)

10: 3.4 mA

11: 4 mA

0x1

R/W

[5:0]

Reserved

0x3C

R/W

Part ID Register

Address: 0x7F, Reset: 0x03 or 0x83, Name: Part ID

Table 63. Bit Descriptions for Part ID

Bits

Bit Name

Description

Reset

Access

[7:0]

Part ID

Version information

0x07 = the AD9129 (14-bit version)

0x87 = the AD9119 (11-bit version)

0x07

0x87

AD9119BBCZ датащи(PDF) 65 Page - Analog Devices

AD9119BBCZ датащи(HTML) 65 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

датащи скачать

ссылки URL