AD9119BBCZ datasheet(37/66 Pages) AD

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Data Sheet

AD9119/AD9129

Rev. B | Page 37 of 66

MSB/LSB TRANSFERS

The AD9119/AD9129 serial port can support both MSB-first

and LSB-first data formats. This functionality is controlled by

the LSB/MSB bit, Bit 6 in Register 0x00. The default is MSB first

(LSB/MSB = 0). When the MSB-first data format is selected, the

instruction and data bytes must be written from the most

significant bit to the least significant bit.

When LSB/MSB = 1 (LSB first), the instruction and data bytes

must be written from the least significant bit to the most

significant bit.

SERIAL PORT CONFIGURATION

The AD9119/AD9129 serial port configuration is controlled

by Register 0x00, Bits[7:5]. Note that the configuration changes

immediately upon writing to the last bit of the register. When

setting the software reset bit (SoftReset in Register 0x00, Bit 5),

all registers are set to their default values except Register 0x00,

which remains unchanged.

In the event of unexpected programming sequences, the

AD9119/AD9129 SPI can become inaccessible. For example,

if user code inadvertently changes the LSB/MSB bit, the bits that

follow experience unexpected results. The SPI can be returned

to a known state by writing an incomplete byte (1 to 7 bits) of

all 0s, followed by three bytes of 0x00. This returns to the MSB-

first instructions (Register 0x00 = 0x00) so that the device can

be reinitialized.

R/W A6

A1 A0 D7N D6N D5N

D00

D10

D20

D30

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

SCLK

SDIO

Figure 122. Serial Register Interface Timing, MSB-First Write

R/W A6

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

SCLK

SDIO

SDO

D6N D5N

D00

D10

D20

D30

D6N D5N

D00

D10

D20

D30

Figure 123. Serial Register Interface Timing, MSB-First Read

A5 A6

R/W

SCLK

SDIO

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

D7N

D6N

D5N

D00 D10 D20

D40

Figure 124. Serial Register Interface Timing, LSB-First Write

R/W

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

SCLK

SDIO

SDO

D7N

D6N

D5N

D10 D20

D40

D7N

D6N

D5N

D10 D20

D40

Figure 125. Serial Register Interface Timing, LSB-First Read

INSTRUCTION BIT 6

INSTRUCTION BIT 7

SCLK

SDIO

tDS

tDH

tSCLK

Figure 126. Timing Diagram for an SPI Register Write

tDV

tDNV

SCLK

SDIO

Figure 127. Timing Diagram for an SPI Register Read

After the last instruction bit is written to the SDIO pin, the

driving signal must be set to a high impedance in time for the

bus to turn around. The serial output data from the AD9119/

AD9129 is enabled by the falling edge of SCLK. This causes the

first output data bit to be shorter than the remaining data bits,

as shown in Figure 127. To assure proper reading of data, read

the SDIO pin or the SDO pin before changing SCLK from low

to high. Due to the more complex multibyte protocol, multiple

AD9119/ AD9129 devices cannot be daisy-chained on the SPI bus.

Control multiple DACs by using independent CS signals.

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