AD9119BBCZ datasheet(42/66 Pages) AD

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AD9119/AD9129

Data Sheet

Rev. B | Page 42 of 66

For the AD9119, the data port is 11-bit instead of 14-bit, so

P0_D11, P0_D12, P0_D13, P1_D11, P1_D12, and P1_D13 are

not used in the calculation of the parity bit. Thus, the parity bit

is calculated over 29 bits (including the frame/parity bit) for the

AD9129 and over 23 bits for the AD9119.

If a parity error occurs, the parity error counter (Register 0x5D

or Register 0x5E) is incremented. Parity errors on the bits that

are sampled by the rising edge of DCI increment the parity

rising edge error counter (Register 0x5D) and set the parity

error rising edge bit (Register 0x5C, Bit 0). Parity errors on the

bits that are sampled by the falling edge of DCI increment the

parity falling edge error counter (Register 0x5E) and set the

parity error falling edge bit (Register 0x5C, Bit 1). The parity

counter continues to accumulate until it is cleared, or until it

reaches a maximum value of 255. The count can be cleared by

writing 1b to Register 0x5C, Bit 5.

An IRQ can be enabled to trigger when a parity error occurs by

writing 1b to Register 0x04, Bit 2 for rising edge-based parity

detection or to Register 0x04, Bit 3 for falling edge-based parity.

The status of IRQ can be measured via Register 0x06, Bit 2 or

pin and more than one IRQ is enabled, check Register 0x06,

Bits[3:2] when an IRQ event occurs to determine whether the

IRQ was caused by a parity error. The IRQ can also be cleared

by writing 1b to Register 0x06, Bit 2 or Register 0x06, Bit 3.

The parity bit feature can also be used to validate the interface

timing. As described previously, the host provides a parity bit

with the data samples and configures the AD9119/AD9129 to

generate an IRQ. The user can then sweep the sampling instance

of the AD9119/AD9129 input registers to determine at what

point a sampling error occurs.

DIGITAL DATAPATH DESCRIPTION

Figure 133 provides a more detailed diagram of the AD9119/

AD9129 digital datapath. The 22-bit/28-bit datapath with

internal DDR clocking interfaces with the dual 11-bit/14-bit

input data ports. Because two 11-bit/14-bit samples are captured

on each clock edge of DCI, four consecutive samples are captured

per DCI clock cycle. Samples captured on the rising edge of DCI

propagate through the upper section at a rate of DACCLK/2

(DDR), and those captured on the falling edge propagate through

the lower section.

PARITY/

SED LOGIC

INPUT

LATCH

INPUT

LATCH

REG 0

REG 1

REG 2

REG 3

REG 4

REG 5

REG 6

REG 7

RESET

LOGIC

FRAME

SPI FIFO ALIGN REQUEST

REG 0x11[7]

SPI FIFO ALIGN ACKNOWLEDGE

REG 0x11[6]

FIFO WRITE POINTER OFFSET

REG 0x12[2:0]

DACCLK/4

DACCLK/4 DIST.

DACCLK/4

DLL

DCI

DATA

FRAME/

PARITY

FRAME

14 BITS

REG 0

REG 1

REG 2

REG 3

REG 4

REG 5

REG 6

REG 7

FIFO PH3

PARITY/

SED LOGIC

TO DAC

DECODE

MIX-MODE

FIFO PH1

FIFO PH2

FIFO PH0

2×

Figure 133. Digital Datapath of the AD9119/AD9129

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