AD9119BBCZ datasheet(41/66 Pages) AD

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Data Sheet

AD9119/AD9129

Rev. B | Page 41 of 66

Maximizing the opening of the eye in both the DCI and data

signals improves reliability of the data port interface. Use differ-

ential controlled impedance traces of equal length (that is, delay)

between the host processor and the AD9119/AD9129 input. To

ensure coincident transitions with the data bits, implement the

DCI as an additional data line with an alternating (010101…)

bit sequence from the same output drivers that are used for

the data.

For synchronous operation between the host and the AD9119/

AD9129, the AD9119/AD9129 provide a data clock output, DCO,

to the host at the same rate as DCI (that is, fDACCLK/4). Note that

the DCI signal can have arbitrary phase alignment with respect to

the DCO because the DLL of the AD9119/AD9129 ensures proper

data hand-off between the two clock domains (that is, the host

processors and the internal digital core of the AD9119/AD9129).

The default reset state of the AD9119/AD9129 is to have the

DCO signal disabled. To enable it, write a 1b to Register 0x0C,

Bit 6. The DCO output level is controlled in Register 0x7C,

Bits[7:6]. The default setting is 01b, or 2.8 mA, but it can be

increased to as high as 4 mA (11b) if higher swing is necessary.

The DCI signal is ac-coupled internally; therefore, a possibility

exists that removing the DCI signal can cause DAC output chatter

due to randomness on the DCI input. To avoid this chatter, it is

recommended that the DAC output be disabled when the DCI

signal is not present. To do this, program the DAC output current

power-down bit in Register 0x01, Bit 6, to 1b. When the DCI signal

is again present, the DAC output can be enabled by programming

The status of the DLL can be polled by reading the data status

and attempting lock, and Bit 7 is set to 1b when the DLL is locked.

Bit 2 is set to 1b when a valid data clock is detected. The warning

bits in Address 0x0E, Bits[6:4] can be used as indicators that the

DAC may be operating in a nonideal location in the delay line.

Note that these bits are read at the SPI port speed, which is much

slower than the actual speed of the DLL. This means that these

bits can show only a snapshot of what is happening, rather than

giving real-time feedback.

Temperature Effects

The length of the delay line varies slightly across the operating

temperature range, as the amount of delay through a delay cell

expands or contracts slightly due to the temperature change.

This can introduce a situation where the DLL may lock at one

temperature extreme and then approach an unlocked state as

the temperature changes (see Figure 132).

In the example shown in Figure 132, the DLL can lock at Phase

Setting 0 at 90° in a cold temperature. As the temperature gets

hotter, the delay line changes length, and the controller adjusts

the DLL control voltage to keep the 90° offset. In this case, a voltage

beyond the acceptable control voltage range is required to hold

the 90° phase offset.

Before losing lock, the DLL controller issues a DLL warning by

setting Register 0x0E, Bit 6, to 1b and setting either Bit 5 or Bit 4

to 1b. This setting indicates that the DLL is near to losing lock. If

the DLL is going to reach the beginning of the delay line soon,

the controller issues a start warning by setting Register 0x0E, Bit 5

and Bit 6 to 1b. This setting indicates that the DLL is at the start

of the delay line, and losing lock is imminent.

USER DCI

USER DATA

DATA

SAMPLE CLK

90°

DELAY LINE – COLD

DELAY LINE

– HOT

Figure 132. Example of DLL Length Variation Across Temperature

A similar situation can happen at the end of the delay line, in

which case a DLL warning and a DLL end is issued. DLL end is

indicated when Register 0x0E, Bit 4 and Bit 6 are set to 1b.

In case of a DLL warning, action must be taken to prevent loss

of lock. On a start warning, reduce the minimum delay of the

delay line by removing one or several of the delay cells. This

can be accomplished by setting the bits in Registers 0x70 and

then Bit 1, and so on. In some cases, up to three delay cells may

need to be disabled. It is possible to disable up to six delay cells.

However, in most cases, none of the cells need to be disabled.

The situation varies, depending on the temperature range needed,

as well as the DACCLK signal rate used. The end warning case

is a theoretical possibility, but practical conditions normally

dictate that it is not reachable. If the end warning is reached, the

DLL must be relocked immediately. When doing initial lock (or

relock) of the DLL, all delay cells must be active, with all delay cell

bits in Register 0x70 and Register 0x71 set to 1b.

Parity

The data interface can be continuously monitored by enabling

the parity bit feature in Register 0x5C, Bit 7, and configuring

the FRM_P, FRM_N pins (Pin K13 and Pin K14) as parity pins

by setting Register 0x07, Bits[1:0] = 1 dec. When this pin con-

figuration is used, the host sends a parity bit along with each data

sample. This bit is set according to the following formulas,

where n is the data sample that is being checked.

For even parity on the AD9129,

XOR[FRM(n), P0_D0(n), P0_D1(n), P0_D2(n), ..., P0_D13(n),

P1_D0(n), P1_D1(n), P1_D2(n), …, P1_D13(n)] = 0.

For odd parity on the AD9129,

XOR[FRM(n), P0_D0(n), P0_D1(n), P0_D2(n), ..., P0_D13(n),

P1_D0(n), P1_D1(n), P1_D2(n), …, P1_D13(n)] = 1.

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