AD9119BBCZ datasheet(45/66 Pages) AD

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Data Sheet

AD9119/AD9129

Rev. B | Page 45 of 66

AD9129

MASTER

DACCLK

MATCHED

DELAYS

DCI

ADCLK925

1.4GHz

2.8GHz

COMMON

CLOCK

SOURCE

DCO_x

FPGA

DCI_x

FRM_x

AD9129

SLAVE

DACCLK

DCO_x

DCI_x

FRM_x

0+ dBm

Figure 136. Example of Synchronization of Two DACs to One FPGA

Data Assembler and Signal Processing Modes

The data assembler reconstructs the original sample sequence.

It consists of a 4:1 multiplexer operating at fDACCLK. Each of the

four FIFOs provides a sample that is now referenced to the

internal clock domain of the AD9119/AD9129, fDACCLK. The

reconstructed sample sequence can be directed to the DAC

decode logic or undergo additional signal processing. In 2×

interpolation mode, a FIR filter is used to generate a new data

sample that is inserted between each sample, such that it can

update the DAC decode logic on the falling edge of DACCLK.

In Mix-Mode, the complement of each data sample is generated

and inserted after it, such that it also updates the DAC in a similar

manner. The 2× interpolator can be used with Mix-Mode enabled.

2× Digital Filter

The AD9119/AD9129 include a bypassable 2× half-band

interpolation filter to help simplify the analog reconstruction

filter. The filter has the potential benefit of minimizing the

impact of folded back harmonics in the desired baseband

region. The filter operates in a dual-edge clocking mode, where

it generates a new interpolated sample value for every alternate

DACCLK edge. This effectively increases the DAC update rate

to 2 × fDACCLK with the DAC’s sinc response null moving from

fDACCLK to 2 × fDACCLK.

There are two different filters, FIR25 and FIR40, that can be

chosen using Register 0x18, Bit 5, when the 2× interpolator is

enabled with Register 0x18, Bit 7.

The FIR25 half-band filter provides 25 dB of stop-band rejection.

Its response is shown in Figure 137. Coefficients were optimized

for practical implementation purposes with the notion that the

±0.5 dB pass-band ripple effects on a multicarrier application

(for example, DOCSIS) can be compensated by the digital host

adjusting individual channel powers. Note that the worst-case

tilt across any 6 MHz channel is less than −0.05 dB.

The FIR40 half-band filter provides 40 dB of stop-band rejection,

and its response is shown in Figure 139. Coefficients were

chosen to reduce pass-band ripple and increase out-of-band

rejection for multicarrier applications (for example, DOCSIS).

As a result, the frequency response has a flatter in-band response

and a sharper transition region, and the trade-off is a higher phase

count, leading to higher pipeline delay and higher power

consumption. The two filters are compared in Table 12.

Table 12. Features of the Two 2× Interpolation Filters

Filter

Ripple (dB)

Attenuation (dB)

Power (mW)

FIR25

±0.5

150

FIR40

±0.1

450

A duty cycle restore circuit follows the DACCLK clock receiver

to minimize impact of duty cycle errors on image rejection.

500

1000

1500

2000

2500

–50

–45

–40

–35

–30

–25

–20

–15

–10

–5

FREQUENCY (MHz)

Figure 137. FIR25 2× Interpolation Filter Plot, Complete Frequency Response;

fDAC = 2.5 GHz

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