AD9119BBCZ datasheet(56/66 Pages) AD

56 / 66 page

AD9119/AD9129

Data Sheet

Rev. B | Page 56 of 66

DEVICE CONFIGURATION REGISTER DESCRIPTIONS

SPI Communications Control Register

Address: 0x00, Reset: 0x81, Name: Mode

Table 18. Bit Descriptions for Mode

Bits

Bit Name

Description

Reset

Access

SDIO_DIR

Selects 3-wire or 4-wire mode

1: 3-wire bidirectional

0: 4-wire unidirectional

R/W

LSB/MSB

LSB/MSB data packing

1: LSB-first packing

0: MSB-first packing

R/W

SoftReset

1: performs a software-based reset

R/W

Reserved

Must be set to 0; reserved (short addressing mode)

R/W

Reserved

Mirror Bit 4 for safety

SoftReset

Mirror Bit 5 for safety

LSB/MSB

Mirror Bit 6 for safety

SDIO_DIR

Mirror Bit 7 for safety

Power Control Register

Address: 0x01, Reset: 0x48, Name: Power-Down

Table 19. Bit Descriptions for Power-Down

Bits

Bit Name

Description

Reset

Access

BG_PD

Band gap power-down

1: band gap is powered down

0: band gap is active

R/W

IREF_PD

IREF power-down

1: FSC is 0 mA

0: FSC is as programmed

R/W

BIAS_PD

Bias power-down

1: all bias currents are off

0: all bias currents are on

R/W

Reserved

R/W

Reserved

Must be set to 1; reserved

R/W

CLKPATH_PD

Clock path power-down

1: DAC clock is powered down

0: DAC clock is active

R/W

Retimer_PD

1: PLL is powered down

R/W

DLL_PD

DLL (data receiver) power-down

1: DLL (data receiver) is powered down

R/W

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