S71PL129JC0 datasheet(78/149 Pages) SPANSION

78 / 149 page

S29PL129J for MCP

S29PL129J_MCP_00_A0 June 4, 2004

Advance

Info rmation

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 100,000 cycles. Additionally,

programming typicals assume checkerboard pattern. All values are subject to change.

2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. All values are subject to change.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most

bytes program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program

command. See Table 12 for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 100,000 cycles.

BGA Pin Capacitance

Notes:

1. Sampled, not 100% tested.

2. Test conditions TA = 25°C, f = 1.0 MHz.

Figure 23. Timing Diagram for Alternating Between CE1# and CE2# Control

Table 25. Erase And Programming Performance

Parameter

Typ (Note 1)

Max (Note 2)

Unit

Comments

Sector Erase Time

0.5

sec

Excludes 00h programming

prior to erasure (Note 4)

Chip Erase Time

PL129J

135

216

sec

Word Program Time

100

µs

Excludes system level

overhead (Note 5)

Accelerated Word Program Time

µs

Chip Program Time

(Note 3)

PL129J

50.4

200

sec

Parameter Symbol

Parameter Description

Test Setup

Typ

Max

Unit

CIN

Input Capacitance

VIN = 0

6.3

COUT

Output Capacitance

VOUT = 0

7.0

CIN2

Control Pin Capacitance

VIN = 0

5.5

CIN3

WP#/ACC Pin Capacitance

VIN = 0

CE1#

tCCR

CE2#

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