S71PL129JC0 datasheet(41/149 Pages) SPANSION

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June 4, 2004 S29PL129J_MCP_00_A0

S29PL129J for MCP

Advance

Informatio n

Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing

provides data protection against inadvertent writes. In addition, the following

hardware data protection measures prevent accidental erasure or programming,

which might otherwise be caused by spurious system level signals during VCC

power-up and power-down transitions, or from system noise.

Low VCC Write Inhibit

When VCC is less than VLKO, the device does not accept any write cycles. This pro-

tects data during VCC power-up and power-down. The command register and all

internal program/erase circuits are disabled, and the device resets to the read

mode. Subsequent writes are ignored until VCC is greater than VLKO. The system

must provide the proper signals to the control pins to prevent unintentional writes

when VCC is greater than VLKO.

Write Pulse “Glitch” Protection

Noise pulses of less than 3 ns (typical) on OE#, CE1#, CE2# or WE# do not ini-

tiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# = VIL, CE1# = CE2# = VIH

or WE# = VIH. To initiate a write cycle, CE1# / CE2# and WE# must be a logical

zero while OE# is a logical one.

Power-Up Write Inhibit

If WE# = CE# (CE1#, CE2# in PL129J) = VIL and OE# = VIH during power up,

the device does not accept commands on the rising edge of WE#. The internal

state machine is automatically reset to the read mode on power-up.

Figure 3. Secured Silicon Sector Protect Verify

Write 60h to

any address

Write 40h to SecSi

Sector address

with A6 = 0,

A1 = 1, A0 = 0

START

RESET# =

VIH or VID

Wait 1

µs

Read from SecSi

Sector address

with A6 = 0,

A1 = 1, A0 = 0

If data = 00h,

SecSi Sector is

unprotected.

If data = 01h,

SecSi Sector is

protected.

Remove VIH or VID

from RESET#

Write reset

command

SecSi Sector

Protect Verify

complete

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