S71PL129JC0 datasheet(60/149 Pages) SPANSION

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S29PL129J for MCP

S29PL129J_MCP_00_A0 June 4, 2004

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Info rmation

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular

sector is actively erasing (that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit II is valid after the rising

edge of the final WE# pulse in the command sequence.

DQ2 toggles when the system reads at addresses within those sectors that have

been selected for erasure. (The system may use either OE# or CE1# / CE2# to

control the read cycles.) But DQ2 cannot distinguish whether the sector is actively

erasing or is erase-suspended. DQ6, by comparison, indicates whether the device

is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors

are selected for erasure. Thus, both status bits are required for sector and mode

information. See Table 14 to compare outputs for DQ2 and DQ6.

Figure 7 shows the toggle bit algorithm in flowchart form, and the “DQ2: Toggle

Bit II” explains the algorithm. See also “DQ6: Toggle Bit I.” Figure 19 shows the

toggle bit timing diagram. Figure 20 shows the differences between DQ2 and DQ6

in graphical form.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 7 for the following discussion. Whenever the system initially be-

gins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to

determine whether a toggle bit is toggling. Typically, the system would note and

store the value of the toggle bit after the first read. After the second read, the

system would compare the new value of the toggle bit with the first. If the toggle

bit is not toggling, the device has completed the program or erase operation. The

system can read array data on DQ7–DQ0 on the following read cycle.

However, if after the initial two read cycles, the system determines that the toggle

bit is still toggling, the system also should note whether the value of DQ5 is high

(see “DQ5: Exceeded Timing Limits”). If it is, the system should then determine

again whether the toggle bit is toggling, since the toggle bit may have stopped

toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device

has successfully completed the program or erase operation. If it is still toggling,

the device did not completed the operation successfully, and the system must

write the reset command to return to reading array data.

The remaining scenario is that the system initially determines that the toggle bit

is toggling and DQ5 has not gone high. The system may continue to monitor the

toggle bit and DQ5 through successive read cycles, determining the status as de-

scribed in the previous paragraph. Alternatively, it may choose to perform other

system tasks. In this case, the system must start at the beginning of the algo-

rithm when it returns to determine the status of the operation (top of Figure 7).

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has exceeded a specified inter-

nal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the

program or erase cycle was not successfully completed.

The device may output a “1” on DQ5 if the system tries to program a “1” to a

location that was previously programmed to “0.” Only an erase operation can

Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle

bit may stop toggling as DQ5 changes to “1.” See “DQ6: Toggle Bit I” and “DQ2: Tog-

gle Bit II” for more information.

Figure 7. Toggle Bit Algorithm

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