ADF41513

Preliminary Technical Data

Rev. PrL | Page 20 of 33

REGISTER 3 (R3) MAP

FRAC2

Register 3, Bits[27:4] set the FRAC2 value. See the N Divider

and R Counter section for more information. When using a

fixed modulus, FRAC2 is ignored.

FRAC2 REGISTER (R3)

DBB

CONTROL

BITS

24-BIT FRAC2 VALUE (FRAC2)

0

0

0

F1

F2

F3

F4

F5

F6

F8

F7

F9

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

F22

F23

F24

0

)

NOTES

1. DBB = DOUBLE-BUFFERED BITS.

F24

F23

...

F2

F1

FRAC2 WORD

0

0

...

0

0

0

0

0

...

0

1

1

0

0

...

1

0

2

0

0

...

1

1

3

.

.

...

.

.

.

.

.

...

.

.

.

.

.

...

.

.

.

1

1

...

0

0

16,777,212

1

1

...

0

1

16,777,213

1

1

...

1

0

16,777,214

1

1

...

1

1

16,777,215

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7

DB6 DB5

DB4

DB3 DB2

DB1 DB0

C3(0)

C4(0)

C2(0) C1(1)

Figure 24. Register 3 (R3) Map