ADF41513 datasheet(11/33 Pages) AD

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Preliminary Technical Data

ADF41513

Rev. PrL | Page 11 of 33

THEORY OF OPERATION

REFERENCE INPUT

The reference input stage is shown in Figure 12. The reference

input accepts an ac-coupled, single-ended signal. During

power-down, this circuit remains active and draws the same

current from AVDD4 as during normal operation. With no

reference connected, AVDD4 drops to approximately 600 µA.

BUFFER

TO R COUNTER

REFIN

20k

Ω

Figure 12. Reference Input Stage

RF INPUT STAGE

The RF input stage is shown in Figure 13. A 2-stage limiting

amplifier follows the RF input stage to generate the current

mode logic (CML) clock levels needed for the prescaler. The

RFINA and RFINB inputs require dc blocking capacitors to isolate

the 1.65 V bias level from the input signal.

BIAS

GENERATOR

1.65V

GND

AVDD

768Ω

RFINA

RFINB

1pF

EXTERNAL

AC COUPLING

FOR SE INPUT

Figure 13. RF Input Stage

N DIVIDER AND R COUNTER

The N divider is used to divide the RF input signal down to the

PFD frequency (fPFD).

fPFD = REFIN × ((1 + D)/(R × (1 + T)))

(1)

where:

REFIN is the reference input frequency.

D is the REFIN doubler bit (0 or 1).

R is the preset divide ratio of the binary 5-bit programmable

reference counter (1 to 32).

T is the REFIN divide by 2 bit (0 or 1).

The N divider value is generated by a Σ-Δ modulator. The

ADF41513 contains two selectable Σ-Δ modulators. One

modulator has a 25-bit fixed modulus (see Figure 14) and one

has a variable modulus up to 49 bits (see Figure 15). DB28 in

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

FRAC

VALUE

225

INT

VALUE

RF INT DIVIDER

N = INT + FRAC/225

FROM RF

INPUT STAGE

TO PFD

N COUNTER

Figure 14. Fixed Modulus N Divider

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

MOD2

VALUE

INT

REG

FRAC2

VALUE

FRAC1

REG

RF INT DIVIDER

FROM RF

INPUT STAGE

TO PFD

N COUNTER

N = INT +

FRAC1 +

FRAC2

MOD2

Figure 15. Variable Modulus N Divider

25-Bit Fixed Modulus (R0, DB28 = 0)

For the 25-bit fixed modulus, the RF VCO frequency (RFOUT)

equation is

RFOUT = fPFD × (INT + (FRAC/225))

(2)

where:

RFOUT is the RF VCO frequency.

INT is a 16-bit value set by DB[19:4] in Register 0

(23 to 65535 for 4⁄5 prescaler, 75 to 65,535 for 8⁄9 prescaler).

FRAC is a 25-bit value set by DB[28:4] in Register 1.

The minimum RF output resolution is set by fPFD∕225. For

example, if fPFD = 100 MHz, the minimum resolution is 2.98 Hz.

By default, due to the architecture of the Σ-Δ modulator, there is

a fixed (fPFD/226) offset added or subtracted from the

programmed output frequency. To remove this offset, set

LSB_P1 (Register 5, DB24).

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