ADF41513 datasheet(12/33 Pages) AD

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ADF41513

Preliminary Technical Data

Rev. PrL | Page 12 of 33

Variable Modulus (R0, DB28 = 1)

For the variable modulus, the RF VCO frequency (RFOUT)

equation is

RFOUT = fPFD × (INT + (FRAC1 + (FRAC2/MOD2))/225) (3)

where:

RFOUT is the output frequency of external VCO.

INT is a 16-bit value set by DB[19:4] in Register 0 (23 to 65,535

for 4⁄5 prescaler, 75 to 65,535 for 8⁄9 prescaler).

FRAC1 is a 25-bit value set by DB[28:4] in Register 1.

FRAC2 is a 24-bit value set by DB[27:4] in Register 3.

MOD2 is a 24-bit value set by DB[27:4] in Register 4.

The minimum RF output resolution is set by fPFD/249. Therefore,

for fPFD = 100 MHz, the minimum resolution is 0.1776 µHz. To

achieve this resolution, MOD2 must be set to its maximum

(224 − 1), 16,777,215.

R COUNTER

The 5-bit R counter allows the REFIN to be divided down to

produce the reference clock to the PFD. Division ratios from 1

to 32 are allowed.

PFD AND CHARGE PUMP

The PFD takes inputs from the R counter and N counter and

produces an output proportional to the phase and frequency

difference between these inputs. Figure 16 shows a PFD simplified

schematic. The PFD includes a fixed delay element that sets the

width of the antibacklash pulse, which is typically 1 ns. This pulse

ensures that there is no dead zone in the PFD transfer function

and gives a consistent reference spur level.

CLR2

DOWN

HIGH

–IN

+IN

CHARGE

PUMP

DELAY

CLR1

Figure 16. PFD Simplified Schematic

MUXOUT

The output multiplexer on the ADF41513 allows the user to access

various internal nodes on the chip. The M4, M3, M2, and M1 bits

in Register 12 (see the Register 12 (R12) Map section) controls

the state of MUXOUT. Figure 17 shows the MUXOUT section in

block diagram form. Many of these access points are useful for

debug. For example, select the N divider output to check if the

N divider is functioning correctly. Most of the access points are

self explanatory. Set the CLK1 divider output signal to access the

internal CLK1 divider signal used for phase resync. During

power-down (CE = logic low), MUXOUT is set to GND.

THREE-STATE OUTPUT

GND

R DIVIDER OUTPUT

N DIVIDER OUTPUT

DIGITAL LOCK DETECT

SERIAL DATA OUTPUT

CLK1 DIVIDER OUTPUT

R DIVIDER/2

MUX

CONTROL

MUXOUT

DVDD

GND

N DIVIDER/2

READBACK

DVDD

Figure 17. MUXOUT Schematic

LOCK DETECTOR

The lock detector compares the PFD output pulse width against

a lock detector window. Measurements are performed every

PFD comparison cycle when LD CLK SEL = 0 or every 32nd

cycle when LD CLK SEL = 1. If the pulse width falls within the

lock window, a counter is incremented. If the counter reaches

the count set by LD COUNT without an up or down pulse

width exceeding the lock detect window and without a cycle slip

occurring, the lock detect is declared.

When the lock detector has declared lock, the main mechanism

to declare a loss of lock is for a cycle slip to occur. This cycle slip

is usually caused by a frequency error at the phase detector

input, causing the phase error to grow until the error exceeds

360°. The phase error then wraps around to 0°. This phase wrap

around is a cycle slip.

A high level on MUXOUT indicates the PLL is in lock.

The lock detector window size, LD COUNT, and LD CLK SEL

all affect the sensitivity of the lock detector. Larger windows,

smaller LD COUNT values, and LD CLK SEL = 0 shorten the

overall lock detect time and increase sensitivity. Smaller

windows, larger LD COUNT values, and LD CLK SEL = 1

increase the overall lock detect time and reduce sensitivity.

Excessive lock detector sensitivity can cause multiple transitions

between a locked state and out of lock state during frequency

changes. Insufficient lock detector sensitivity can cause the

detector to indicate an out of lock state when, in fact, the PLL is

locked.

The window size can be adjusted between 0.9 ns and 11.5 ns

with LDP, Bits[9:8] in Register 6 and LD BIAS, Bits[31:30] in

maximum window, set by the phase comparison period, tPFD

(10 ns for 100 MHz reference and R = 1), and the minimum is

set by

(IBLEED/ICP) × tPFD

(4)

LD COUNT can range from 2 counts to 8192 counts. The

fastest lock indication requires two measurement cycles (20 ns

with 100 MHz reference, R = 1, and LD CLK SEL = 0). In

practice, the lock indication takes much longer because of the

loop filter on the phase comparator. When LD CLK SEL = 1, a

minimum 64 measurements are required (640 ns).

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