ADF41513 datasheet(4/33 Pages) AD

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ADF41513

Preliminary Technical Data

Rev. PrL | Page 4 of 33

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

POWER SUPPLIES

AVDD1, AVDD2, AVDD3, AVDD4, AVDD5, VP

3.135

3.3

3.465

IDD13

0.3

Current drawn by AVDD1

IDD24

63.5

Current drawn by AVDD2

IDD35

2.1

Current drawn by AVDD3

IDD46

2.6

Current drawn by AVDD4

IDD57

1.7

Current drawn by AVDD5

4.5

Current drawn by VP

Power-Down Mode

0.4

µA

TA = 25°C, CE = low, total of all rails

NOISE CHARACTERISTICS

Normalized Phase Noise Floor

(PNSYNTH)8 in Integer N Mode

−234

dBc/Hz

PLL loop bandwidth (BW) = 1 MHz (integer N

mode)

Normalized Phase Noise Floor

(PNSYNTH)5 in Fractional-N Mode

−231

dBc/Hz

PLL loop BW = 1 MHz (fractional-N mode)

Normalized 1∕f Noise (PN1_f)9

−127

dBc/Hz

10 kHz offset, normalized to 1 GHz

SPURIOUS SIGNALS

Reference Spurious

−90

dBc

At reference = 100 MHz

PFD Spurious

−87

dBc

At PFD = 50 MHz

In-Band Integer Boundary

Spurious

−45

dBc

10 kHz offset, PLL loop BW = 250 kHz

This is the maximum operating frequency of the N counter. Ensure that the RF input divides down to a frequency that is less than this value by choosing a prescaler

value that is less than the maximum operating frequency of the N counter.

AC coupling ensures 1 V bias.

TA = 25°C, AVDD1 = 3.3 V, prescaler (P) = 8/9, fRFIN = 12.0 GHz, REFIN = 100 MHz, PFD frequency input (fPFD) = 100 MHz.

TA = 25°C, AVDD2 = 3.3 V, P = 8/9, fRFIN = 12.0 GHz, REFIN = 100 MHz, fPFD = 100 MHz.

TA = 25°C, AVDD3 = 3.3 V, P = 8/9, fRFIN = 12.0 GHz, REFIN = 100 MHz, fPFD = 100 MHz.

TA = 25°C, AVDD4 = 3.3 V, P = 8/9, fRFIN = 12.0 GHz, REFIN = 100 MHz, fPFD = 100 MHz.

TA = 25°C, AVDD5 = 3.3 V, P = 8/9, fRFIN = 12.0 GHz, REFIN = 100 MHz, fPFD = 100 MHz.

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider

value) and 10 log fPFD. PNSYNTH = total phase noise measured at the VCO output (PNTOT) − 10 log fPFD − 20 log N.

The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF,

and at a frequency offset, f, is given by phase noise (PN) = P1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are

modeled in the ADIsimPLL.

TIMING CHARACTERISTICS

AVDDX = VP = 3.3 V ± 5%, GND = 0 V, RSET = 2.7 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted.

Table 2. Read and Write Timing

Parameter

Limit at TMIN to TMAX

Unit

Test Conditions/Comments

ns min

LE setup time

ns min

DATA to CLK setup time

ns min

DATA to CLK hold time

ns min

CLK high duration

ns min

CLK low duration

ns min

CLK to LE setup time

ns min

LE pulse width

ns min

LE setup time to MUXOUT when MUXOUT is configured as SPI output

ns min

CLK setup time to MUXOUT when MUXOUT is configured as SPI output

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