ADF41513 datasheet(32/33 Pages) AD

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ADF41513

Preliminary Technical Data

Rev. PrL | Page 32 of 33

SPUR MECHANISMS

This section describes the two different spur mechanisms that

arise with a PLL, and how to minimize them in the ADF41513.

Integer Boundary Spurs

Interactions between the RF VCO frequency and the reference

frequency cause integer boundary spurs. When these

frequencies are not integer related (the point of a fractional-N

synthesizer), spur sidebands appear on the VCO output

spectrum at an offset frequency that corresponds to the beat

note or difference frequency between an integer multiple of the

reference and the VCO frequency. These spurs are attenuated by

the loop filter and are more noticeable on channels close to

integer multiples of the reference where the difference

frequency can be inside the loop bandwidth. Therefore, the

name integer boundary spurs.

Reference Spurs

Reference spurs are generally not a problem in fractional-N

synthesizers because the reference offset is far outside the loop

bandwidth. However, any reference feedthrough mechanism

that bypass the loop can cause a problem. Feedthrough of low

levels of on-chip reference switching noise, through the RFINA

pin or the RFINB pin back to the VCO, can result in reference

spur levels as high as −90 dBc. PCB layout must ensure

adequate isolation between VCO traces and the input reference

to avoid a possible feedthrough path on the board.

PHASE RESYNC

The output of a 25-bit fractional-N PLL can settle to any of the

225 phase offsets with respect to the input reference. The phase

resync feature in the ADF41513 produces a consistent output

phase offset with respect to the input reference. This consistent

output phase offset with respect to the input reference is necessary

in applications where the output phase and frequency are

important, such as digital beam forming. See the Phase

Programmability section to program a specific RF output phase

when using phase resync.

Phase resync is enabled by setting Register 7, Bits[19:18] =

0b10. When phase resync is enabled, an internal timer generates

sync signals at intervals of tSYNC given by the following formula:

tSYNC = CLK1 × CLK2 × tPFD

(9)

where:

CLK1 is the decimal value programmed in Register 5, Bits[15:4].

CLK2 is the decimal value programmed in Register 7, Bits[17:6],

while Register 7, Bits[5:4] = 0b00

tPFD is the PFD reference period (1/fPFD).

When a new frequency is programmed, the second sync pulse

after the LE rising edge resynchronizes the output phase to the

reference. Program the tSYNC time to a value that is at least as

long as the worst case lock time to guarantee that the phase

resync occurs after the last cycle slip in the PLL settling

transient.

In the example shown in Figure 35, tSYNC is set to 550 µs. The

second sync pulse and any later sync pulses are ignored.

PHASE

FREQUENCY

SYNC

(INTERNAL)

–100

100

200

1000

300

400

500

600

700

800

900

TIME (µs)

PLL SETTLES TO

CORRECT PHASE

AFTER RESYNC

LAST CYCLE SLIP

PLL SETTLES TO

INCORRECT PHASE

Figure 35. Phase Resync Example

Phase Programmability

The phase word in Register 2 controls the RF output phase. As

this word is changed from 0 to 212, the RF output phase changes

over a 360° range in steps of Phase Value × 360°/212.

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