AD9554BCPZ datasheet(2/116 Pages) AD

2 / 116 page

AD9554

Data Sheet

Rev. D | Page 2 of 116

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 4

Specifications..................................................................................... 5

Supply Voltage............................................................................... 5

Supply Current.............................................................................. 5

Power Dissipation......................................................................... 6

System Clock Inputs (XOA, XOB) ............................................. 6

Reference Inputs ........................................................................... 7

Reference Monitors ...................................................................... 8

Reference Switchover Specifications.......................................... 8

Distribution Clock Outputs ........................................................ 9

Time Duration of Digital Functions ........................................ 11

Digital PLL (DPLL_0, DPLL_1, DPLL_2, and DPLL_3) ...... 11

Analog PLL (APLL_0, APLL_1, APLL_2, and APLL_3) ...... 11

Digital PLL Lock Detection ...................................................... 12

Holdover Specifications............................................................. 12

Serial Port Specifications—Serial Port Interface (SPI) Mode12

Serial Port Specifications—I2C Mode ...................................... 13

Logic Inputs (RESET, M9 to M0)............................................. 14

Logic Outputs (M9 to M0)........................................................ 14

Jitter Generation ......................................................................... 15

Absolute Maximum Ratings.......................................................... 16

ESD Caution................................................................................ 16

Pin Configuration and Function Descriptions........................... 17

Typical Performance Characteristics ........................................... 21

Input/Output Termination Recommendations .......................... 24

Getting Started ................................................................................ 25

Chip Power Monitor and Startup............................................. 25

Multifunction Pins at Reset/Power-Up ................................... 25

Device Register Programming Using a Register Setup File.. 25

Theory of Operation ...................................................................... 33

Overview...................................................................................... 33

Reference Input Physical Connections.................................... 34

Reference Monitors .................................................................... 34

Reference Input Block................................................................ 34

Reference Switchover ................................................................. 35

Digital PLL (DPLL) Core .......................................................... 35

Loop Control State Machine..................................................... 38

System Clock (SYSCLK)................................................................ 39

SYSCLK Inputs ........................................................................... 39

SYSCLK Multiplier..................................................................... 39

Output Analog PLL (APLL).......................................................... 41

APLL Configuration .................................................................. 41

APLL Calibration ....................................................................... 41

Clock Distribution.......................................................................... 42

Clock Dividers ............................................................................ 42

Output Amplitude and Power-Down ...................................... 42

Clock Distribution Synchronization........................................ 43

Status and Control.......................................................................... 44

Multifunction Pins (M0 to M9) ............................................... 44

IRQ Function .............................................................................. 44

Watchdog Timer......................................................................... 45

EEPROM ..................................................................................... 45

Serial Control Port ......................................................................... 49

SPI/I2C Port Selection................................................................ 49

SPI Serial Port Operation.......................................................... 49

I2C Serial Port Operation .......................................................... 52

Programming the Input/Output Registers.................................. 55

Buffered/Active Registers.......................................................... 55

Write Detect Registers ............................................................... 55

Autoclear Registers..................................................................... 55

Thermal Performance.................................................................... 56

Power Supply Partitions................................................................. 57

VDD Supplies ............................................................................. 57

VDD_SP Supply ......................................................................... 57

Serial Control Port Configuration (Register 0x0000 to

Clock Part Family ID (Register 0x0003 to Register 0x0006) 71

SPI Version (Register 0x000B).................................................. 71

Vendor ID (Register 0x000C to Register 0x000D) ................ 71

IO_Update (Register 0x000F)................................................... 71

User Scratchpad (Register 0x00FE to Register 0x00FF) ....... 71

AD9554BCPZ датащи(PDF) 2 Page - Analog Devices

AD9554BCPZ датащи(HTML) 2 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL