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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9554BCPZ датащи(PDF) 60 Page - Analog Devices |
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AD9554BCPZ датащи(HTML) 60 Page - Analog Devices |
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60 / 116 page  AD9554 Data Sheet Rev. D | Page 60 of 116 Reg Addr (Hex) Option Name D7 D6 D5 D4 D3 D2 D1 D0 Def (Hex) 0x0301 W1, L REFA R divider (20 bits) R divider, Bits[7:0] 0x00 0x0302 W1, L R divider, Bits[15:8] 0x00 0x0303 W1, L Reserved R divider, Bits[19:16] 0x00 0x0304 W2, L REFA period Nominal reference period (fs), Bits[7:0] 0x00 0x0305 W2, L Nominal reference period (fs), Bits[15:8] 0x00 0x0306 W2, L Nominal reference period (fs), Bits[23:16] 0x00 0x0307 W2, L Nominal reference period (fs), Bits[31:24] 0x00 0x0308 W2, L Nominal reference period (fs), Bits[39:32] 0x00 0x0309 W2, L REFA frequency tolerance Inner tolerance (1/(ppm error)), Bits[7:0] (for invalid to valid condition; maximum: 6.55%, minimum: 2 ppm) (default: 5%) 0x14 0x030A W2, L Inner tolerance (1/(ppm error)), Bits[15:8] (for invalid to valid condition; maximum: 6.55%, minimum: 2 ppm) 0x00 0x030B W2, L Reserved Inner tolerance (1/(ppm error)), Bits[19:16] 0x00 0x030C W2, L Outer tolerance (1/(ppm error)), Bits[7:0] (for valid to invalid; maximum: 6.55%, minimum: 2 ppm) (default: 10%) 0x0A 0x030D W2, L Outer tolerance (1/(ppm error)), Bits[15:8] (for valid to invalid; max: 6.55%, min: 2 ppm) 0x00 0x030E W2, L Reserved Outer tolerance (1/(ppm error)), Bits[19:16] 0x00 0x030F W2, L REFA validation timer Validation timer (ms), Bits[7:0] (up to 65.5 sec) 0x0A 0x0310 W2, L Validation timer (ms), Bits[15:8] (up to 65.5 sec) 0x00 0x0311 W3, L REFA phase lock detector Phase lock threshold (ps), Bits[7:0] 0xBC 0x0312 W3, L Phase lock threshold (ps), Bits[15:8] 0x02 0x0313 W3, L Phase lock threshold (ps), Bits[23:16] 0x00 0x0314 W3, L Phase lock fill rate, Bits[7:0] 0x0A 0x0315 W3, L Phase lock drain rate, Bits[7:0] 0x0A 0x0316 W3, L REFA frequency lock detector Frequency lock threshold (ps), Bits[7:0] 0xBC 0x0317 W3, L Frequency lock threshold (ps), Bits[15:8] 0x02 0x0318 W3, L Frequency lock threshold (ps), Bits[23:16] 0x00 0x0319 W3, L Frequency lock fill rate, Bits[7:0] 0x0A 0x031A W3, L Frequency lock drain rate, Bits[7:0] 0x0A 0x031B W3, L REFA phase step threshold Phase step threshold (ps), Bits[7:0] 0x00 0x031C W3, L Phase step threshold (ps), Bits[15:8] 0x00 0x031D W3, L Phase step threshold (ps), Bits[23:16] 0x00 0x031E W3, L Reserved Phase step threshold (ps), Bits[27:24] 0x00 Reference Input B 0x0320 to 0x033E These registers mimic the Reference Input A registers (0x0300 through 0x031E) but the register addresses are offset by 0x0020. All default values are identical. Reference Input C 0x0340 to 0x035E These registers mimic the Reference Input A registers (0x0300 through 0x031E) but register addresses are offset by 0x0040. All default values are identical. Reference Input D 0x0360 to 0x037E These registers mimic the Reference Input A registers (0x0300 through 0x031E) but the register addresses are offset by 0x0060. All default values are identical. DPLL_0 General Settings 0x0400 DPLL_0 free run frequency TW 30-bit free running frequency tuning word, Bits[7:0] 0x00 0x0401 30-bit free running frequency tuning word, Bits[15:8] 0x00 0x0402 30-bit free running frequency tuning word, Bits[23:16] 0x00 0x0403 Reserved 30-bit free running frequency tuning word, Bits[29:24] 0x00 0x0404 DPLL_0 DCO integer Reserved DCO integer, Bits[3:0] 0x17 0x0405 DPLL_0 frequency clamp Lower limit of pull-in range, Bits[7:0] 0xCC 0x0406 Lower limit of pull-in range, Bits[15:8] 0xCC 0x0407 Reserved Lower limit of pull-in range, Bits[19:16] 0x00 0x0408 Upper limit of pull-in range, Bits[7:0] 0x33 0x0409 Upper limit of pull-in range, Bits[15:8] 0x33 0x040A Reserved Upper limit of pull-in range, Bits[19:16] 0x0F 0x040B DPLL_0 holdover history History accumulation timer (ms), Bits[7:0] (up to 65 sec) 0x0A 0x040C History accumulation timer (ms), Bits[15:8] (up to 65 sec) 0x00 |
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