AD9554BCPZ datasheet(44/116 Pages) AD

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AD9554

Data Sheet

Rev. D | Page 44 of 116

STATUS AND CONTROL

MULTIFUNCTION PINS (M0 TO M9)

The AD9554 has ten digital CMOS input/output pins (M0 to

M9) that are configurable for a variety of uses. The function of

these pins is programmable via the register map. Each pin can

control or monitor an assortment of internal functions based on

The Mx pins feature a special write detection logic that prevents

these pins from behaving unpredictably when the Mx pins function

changes. When the user writes to these registers, the existing

Mx pin function stops. The new Mx pin function takes effect

on the next IO_UPDATE (Register 0x000F = 0x01).

The Mx pins operate in one of four modes: active high CMOS,

active low CMOS, open-drain PMOS, and open-drain NMOS.

Table 23. Mx Pins Four Modes of Operation

Setting

Mode

Description

Active

high

CMOS

When deasserted, the Mx pin is Logic 0.

When asserted, the Mx pin is Logic 1,

which is the default operating mode

Active low

CMOS

When deasserted, the Mx pin is Logic 1.

When asserted, the Mx pin is Logic 0.

Open-

drain

PMOS

When deasserted, the Mx pin is high

impedance.

When the Mx pin is asserted, it is active

high; it requires an external pull-down

resistor.

Open-

drain

NMOS

When deasserted, the Mx pin is high

impedance.

When the Mx pin is asserted, it is active

low; it requires an external pull-up

resistor.

To monitor an internal function with a multifunction pin, write

a Logic 1 to the most significant bit of the register associated

with the desired multifunction pin. The value of the seven least

significant bits of the register defines the control function, as

shown in Table 154.

To control an internal function with a multifunction pin, write a

Logic 0 to the most significant bit of the register associated with

the desired multifunction pin. The monitored function depends

on the value of the seven least significant bits of the register, as

shown in Table 155.

Note that each Mx pin has an open-drain mode that allows the

user to perform logical AND and logical OR functions with the

Mx pin outputs. For instance, it is possible to connect the IRQ

lines of multiple AD9554s on one board together and to make

the IRQ line the logical OR of each AD9554 IRQ line.

It is also possible to have an input function like IRQ clearing to

be the logical combination of multiple inputs. For example, IRQ

clearing is desired only if M2 is high and M3 is low, and either

M0 is high or M1 is low.

In function form, this is the following:

Result = (M0 || !M1) && M2 && !M3

To accomplish this, set the M0 through M3 pins as the IRQ clearing

function, and set the Mx pin modes of operation as the following:



M0 = OR true signal (Register 0x100[1:0] = 10)



M1 = OR inverted signal (Register 0x100[3:2] = 11)



M2 = AND true signal (Register 0x100[5:4] = 00)



M3 = AND inverted signal (Register 0x100[7:6] = 01)

IRQ FUNCTION

The AD9554 IRQ function can be assigned to any Mx pin.

There are five IRQ categories: PLL0, PLL1, PLL2, PLL3, and

common. This means an Mx pin can be set to respond only to

IRQs that relate to one of the PLLs or to common functions. An

Mx pin can also be set to respond to all IRQs.

The AD9554 asserts an IRQ when any bit in the IRQ monitor

bit in this register is associated with an internal function that is

capable of producing an interrupt. Furthermore, each bit of the

IRQ monitor register is the result of a logical AND of the associated

internal interrupt signal and the corresponding bit in the IRQ

mask register (Register 0x010F to Register 0x011D). That is, the

bits in the IRQ mask registers have a one-to-one correspondence

with the bits in the IRQ monitor registers. When an internal

function produces an interrupt signal and the associated IRQ

mask bit is set, the corresponding bit in the IRQ monitor register is

set. Be aware that clearing a bit in the IRQ mask register removes

only the mask associated with the internal interrupt signal. It does

not clear the corresponding bit in the IRQ monitor register.

The IRQ function is edge triggered which means that if the

condition that generated an IRQ (for example, loss of DPLL_0

lock) still exists after an IRQ is cleared, the IRQ does not reactivate

until DPLL_0 lock is restored and lost again. However, if the IRQs

are enabled when DPLL_0 is not locked, an IRQ is generated.

The IRQ function of an Mx pin is the result of a logical OR of

all the IRQ monitor register bits. The AD9554 asserts an IRQ as

long as any of the IRQ monitor register bits is a Logic 1. Note

that it is possible to have multiple bits set in the IRQ monitor

registers. Therefore, when the AD9554 asserts an IRQ, it may

indicate an interrupt from several different internal functions. The

IRQ monitor registers provide a way to interrogate the AD9554 to

determine which internal function(s) produced the interrupt.

Typically, when the AD9554 asserts an IRQ, the user interrogates

the IRQ monitor registers to identify the source of the interrupt

request. After servicing an indicated interrupt, the user must

clear the associated IRQ monitor register bit via the IRQ clearing

registers (Address 0x0A05 to Address 0x0A14). The bits in the

IRQ clearing registers have a one-to-one correspondence with

the bits in the IRQ monitor registers.

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