AD9554BCPZ datasheet(13/116 Pages) AD

13 / 116 page

Data Sheet

AD9554

Rev. D | Page 13 of 116

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SDIO

As an Input

Input Logic 1 Voltage

VDD_SP − 0.4

Input Logic 0 Voltage

0.4

Input Logic 1 Current

μA

Input Logic 0 Current

μA

Input Capacitance

As an Output

Output Logic 1 Voltage

VDD_SP − 0.2

1 mA load current

Output Logic 0 Voltage

0.1

1 mA load current

SDO

Output Logic 1 Voltage

VDD_SP − 0.2

1 mA load current

Output Logic 0 Voltage

0.1

1 mA load current

High-Z Leakage Current

±6

±100

μA

TIMING

Valid for VDD_SP = 1.5 V, VDD_SP = 1.8 V, and VDD_SP = 2.5 V

SCLK

Clock Rate, 1/tCLK

MHz

Pulse Width High, tHIGH

Pulse Width Low, tLOW

SDIO to SCLK Setup, tDS

1.5

SCLK to SDIO Hold, tDH

SCLK to Valid SDIO and SDO, tDV

CS to SCLK Setup, tS

CS to SCLK Hold, tC

CS Minimum Pulse Width High

1.5

SERIAL PORT SPECIFICATIONS—I2C MODE

Table 15.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SDA, SCL (AS INPUTS)

Valid for VDD_SP = 1.5 V, VDD_SP = 1.8 V, and

VDD_SP = 2.5 V

Input Logic 1 Voltage

0.7 × VDD_SP

Input Logic 0 Voltage

0.3 × VDD_SP

Input Current

−10

+10

μA

For VIN = 10% to 90% of VDD

Hysteresis of Schmitt Trigger Inputs

0.015 × VDD

SDA (AS OUTPUT)

Output Logic 0 Voltage

0.2

IOUT = 3 mA

Output Fall Time from VIH Minimum

to VIL Maximum

20 + 0.1 × Cb

250

10 pF ≤ Cb ≤ 400 pF

TIMING

SCL Clock Rate

400

kHz

Bus-Free Time Between a Stop and

Start Condition, tBUF

1.3

μs

Repeated Start Condition Setup

Time, tSU; STA

0.6

μs

Repeated Hold Time Start Condition,

tHD; STA

0.6

μs

After this period, the first clock pulse is generated

Stop Condition Setup Time, tSU; STO

0.6

μs

Low Period of the SCL Clock, tLOW

1.3

μs

High Period of the SCL Clock, tHIGH

0.6

μs

SCL/SDA Rise Time, tR

20 + 0.1 × Cb

300

SCL/SDA Fall Time, tF

20 + 0.1 × Cb

300

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