AD9554BCPZ datasheet(96/116 Pages) AD

96 / 116 page

AD9554

Data Sheet

Rev. D | Page 96 of 116

Table 112. PLL_0 User Mode

Address

Bits

Bit Name

Description

0x0A22

Reserved

Default: 0b.

[6:5]

DPLL_0 manual reference

Input reference when user selection mode = 00, 01, 10, or 11.

00 (default) = Input Reference A.

01 = Input Reference B.

10 = Input Reference C.

11 = Input Reference D.

[4:2]

DPLL_0 switching mode

Selects the operating mode of the reference switching state machine.

Reference Switchover

Mode, Bits[2:0]

Reference Selection Mode

000b

Automatic revertive mode

001b

Automatic nonrevertive mode

010b

Manual reference select mode (with automatic fallback)

011b

Manual reference select mode (with holdover fallback)

100b

Manual reference select mode (without holdover fallback)

101b

Not used

110b

Not used

111b

Not used

DPLL_0 user holdover

Forces DPLL_0 into holdover mode. Note that the AD9554 enters free run mode if this bit is

set when there is no holdover history available.

0 (default) = normal operation.

1 = DPLL_0 is forced into holdover mode until this bit is cleared. Note that holdover mode is

used if the holdover history is available. User free run mode is used if the holdover history is

not available. See Register 0x0D22, Bit 0 for the DPLL_0 history available indication.

DPLL_0 user free run

Forces DPLL_0 into free run mode.

0 (default) = normal operation.

1 = DPLL_0 is forced into free run mode until this bit is cleared.

Table 113. PLL_0 Reset

Address

Bits

Bit Name

Description

0x0A23

[7:3]

Reserved

Default: 00000b.

Reset DPLL_0 loop filter

Resets the digital loop filter.

0 (default) = normal operation.

1 = DPLL_0 digital loop filter is reset. This is an autoclearing bit.

Reset DPLL_0 TW history

Resets the tuning word history (part of holdover functionality).

0 (default) = normal operation.

1 = DPLL_0 tuning word history is reset. This is an autoclearing bit.

Reset DPLL_0 autosync

Resets the automatic synchronization logic (see Register 0x0435).

0 (default) = normal operation.

1 = DPLL_0 automatic synchronization logic is reset. This is an autoclearing bit.

Table 114. PLL_0 Phase

Address

Bits

Bit Name

Description

0x0A24

[7:3]

Reserved

Default: 00000b.

DPLL_0 reset phase offset

Resets the incremental phase offset to zero. This is an autoclearing bit.

DPLL_0 decrement phase offset

Decrements the incremental phase offset by the amount specified in the incremental

phase lock offset step size registers (Register 0x0412 and Register 0x0413). This is an

autoclearing bit.

DPLL_0 increment phase offset

Increments the incremental phase offset by the amount specified in the incremental

phase lock offset step size registers (Register 0x0412 and Register 0x0413). This is an

autoclearing bit.

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