AD9554BCPZ datasheet(49/116 Pages) AD

49 / 116 page

Data Sheet

AD9554

Rev. D | Page 49 of 116

SERIAL CONTROL PORT

The AD9554 serial control port is a flexible, synchronous serial

communications port that provides a convenient interface to

many industry-standard microcontrollers and microprocessors.

The AD9554 serial control port is compatible with most

synchronous transfer formats, including I2C, Motorola SPI, and

Intel SSR protocols. The serial control port allows read/write

access to the AD9554 register map.

The AD9554 uses the Analog Devices unified SPI protocol (see

Analog Devices Serial Control Interface Standard). The unified

SPI protocol guarantees that all new Analog Devices products

using the unified protocol have consistent serial port

characteristics. The SPI port configuration is programmable via

rather than in the register map and is distinct from the I2C

Unified SPI differs from the SPI port found on older products

like the AD9557 and AD9558 in the following ways:



Unified SPI does not have byte counts. A transfer is

terminated when the CS pin goes high. The W1 and W0

bits in the traditional SPI become the A12 and A13 bits of

the register address. This is similar to streaming mode in

the traditional SPI.



The address ascension bit (Register 0x0000) controls

whether register addresses are automatically incremented

or decremented regardless of the LSB/MSB first setting. In

traditional SPI, LSB first dictated autoincrements and MSB

first dictated autodecrements of the register address.



Devices that adhere to the unified serial port have a

consistent structure of the first 16 register addresses.

Although the AD9554 supports both the SPI and I2C serial port

protocols, only one is active following power-up (as determined

by the M0, M5, M6, and M7 multifunction pins during the

start-up sequence). The only way to change the serial port

protocol is to reset (or power cycle) the device.

SPI/I²C PORT SELECTION

Because the AD9554 supports both SPI and I2C protocols, the

active serial port protocol depends on the logic state of M0, M5,

M6, and M7 pins at reset or power-on. See Table 22 for the I2C

address assignments.

SPI SERIAL PORT OPERATION

Pin Descriptions

The SCLK (serial clock) pin serves as the serial shift clock. This

pin is an input. SCLK synchronizes serial control port read and

write operations. The rising edge SCLK registers write data bits,

and the falling edge registers read data bits. The SCLK pin

supports a maximum clock rate of 50 MHz.

The SPI port supports both 3-wire (bidirectional) and 4-wire

(unidirectional) hardware configurations and both MSB-first

and LSB-first data formats. Both the hardware configuration

and data format features are programmable. The 3-wire mode

uses the SDIO (serial data input/output) pin for transferring

data in both directions. The 4-wire mode uses the SDIO pin for

transferring data to the AD9554, and the SDO pin for

transferring data from the AD9554.

The CS (chip select) pin is an active low control that gates read

and write operations. Assertion (active low) of the CS pin

initiates a write or read operation to the AD9554 SPI port. Any

number of data bytes can be transferred in a continuous stream.

The register address is automatically incremented or decremented

based on the setting of the address ascension bit (Register 0x0000).

CS must be deasserted at the end of the last byte transferred,

thereby ending the stream mode. This pin is internally

connected to a 10 kΩ pull-up resistor. When CS is high, the

SDIO and SDO pins go into a high impedance state.

Implementation Specific Details

A detailed description of the unified SPI protocol can be found

in the AN-877 Application Note, which covers items such as

timing, command format, and addressing.

The following product specific items are defined in the unified

SPI protocol:



Analog Devices unified SPI protocol revision: 1.0



Chip type: 0x5



Product ID: 0x009



Physical layer: 3- and 4-wire supported and 1.5 V, 1.8 V,

and 2.5 V operation supported



Optional single-byte instruction mode: not supported



Data link: not used



Control: not used

Communication Cycle—Instruction Plus Data

The unified SPI protocol consists of a two-part communication

cycle. The first part is a 16-bit instruction word that is

coincident with the first 16 SCLK rising edges and a payload.

The instruction word provides the AD9554 serial control port

with information regarding the payload. The instruction word

includes the R/W bit that indicates the direction of the payload

transfer (that is, a read or write operation). The instruction

word also indicates the starting register address of the first

payload byte.

AD9554BCPZ датащи(PDF) 49 Page - Analog Devices

AD9554BCPZ датащи(HTML) 49 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL