LTC6955 datasheet(17/22 Pages) AD

17 / 22 page

LTC6955

Rev 0

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

In the third scenario, a perfect sine wave input is buffered

by a noiseless amplifier to drive the ADC. Sampling is

performed by a clock signal with added jitter. Note that

as the signal is slewing, the jitter of the clock signal leads

to an uncertainty in the digitized value and an error term

just as in the previous scenario. Again, this error term

degrades the SNR.

A real-world system will have both additive amplifier noise

and sample clock jitter. Once the signal is digitized, deter-

mining the root cause of any SNR degradation – amplifier

noise or sampling clock jitter – is difficult.

Degradation of the SNR due to sample clock jitter only

occurs if the analog input signal is slewing. If the analog

input signal is stationary (DC) then it does not matter

when in time the sampling occurs. Additionally, a faster

slewing input signal yields a greater error (more noise)

than a slower slewing input signal.

Figure 7 demonstrates this effect. Note how much larger

the error term is with the fast slewing signal than with the

slow slewing signal. To maintain the data converter’s SNR

performance, digitization of high input frequency signals

requires a clock with much less jitter than applications

with lower frequency input signals.

It is important to note that the frequency of the analog

input signal determines the sample clock’s jitter require-

ment. The actual sample clock frequency does not matter.

Many ADC applications that under-sample high frequency

signals have especially challenging sample clock jitter

requirements.

The previous discussion was useful for gaining an intui-

tive feel for the SNR degradation due to sampling clock

jitter.

Quantitatively, the actual sample clock jitter requirement

for a given application is calculated as follows:

tJ(TOTAL) =

−SNRdB

2 •

π • fSIG

(1)

Where fSIG is the highest frequency signal to be digitized

expressed in Hz, SNRdB is the SNR requirement in deci-

bels and tJ(TOTAL) is the total RMS jitter in seconds. The

total jitter is the RMS sum of the ADC’s aperture jitter and

the sample clock jitter calculated as follows:

tJ(TOTAL) = tJ(CLK)

2 + t

J(ADC)

(2)

Alternatively, for a given total jitter, the attainable SNR is

calculated as follows:

SNRdB = −20log10 2 • π • fSIG • tJ(TOTAL)

(

)

(3)

These calculations assume a full-scale sine wave input

signal. If the input signal is a complex, modulated signal

with a moderate crest factor, the peak slew rate of the

signal may be lower and the sample clock jitter require-

ment may be relaxed.

Figure 7. Fast and Slow Sine Wave Signals

Sampled with a Jittery Clock

6955 F07

∆V = VERROR(SLOW)

∆V = VERROR(FAST)

FAST

SINE WAVE

SLOW

SINE WAVE

APPLICATIONS INFORMATION

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