LTC6955 datasheet(11/22 Pages) AD

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LTC6955

Rev 0

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

OPERATION

The LTC6955 is a high-performance multi-output clock

buffer that operates up to 7.5GHz. The device is able to

achieve superior integrated jitter performance by way of

its excellent output noise floor.

Input Buffer

The LTC6955’s input buffer provides a flexible interface to

either differential or single-ended frequency sources. The

inputs are self-biased, and AC-coupling is recommended

for applications using external VCO/VCXO/VCSOs.

However, the input can also be driven DC-coupled by

LVPECL, CML, or any other driver type within the input’s

specified common mode range. See the Applications

Information section for more information on common

input interface configurations, noting that the LTC6955’s

input buffer has an internal differential resistance of 250Ω

as shown in Figure 1.

100V/µs, although better performance will be achieved

with a higher slew rate. For applications with an input slew

rate less than 2V/ns, better phase noise performance will

be achieved by enabling the internal broadband noise fil-

tering circuit within the input buffer. This is accomplished

by setting the FILT pin (pin 40) to V+. Note that setting

FILT = V+ when the slew rate of the input is greater than

2V/ns will degrade the overall phase noise performance.

See Table 1 for recommended settings of FILT.

Table 1. FILT Control Voltage

FILTV

Slew Rate of Input

V+

< 2V/ns

GND

≥ 2V/ns

CML Output Buffers (OUT0 to OUT10)

All of the outputs are ultralow noise, low skew 2.5V CML

buffers. Each output can be AC or DC coupled and termi-

nated with 100Ω differential. If a single-ended output is

desired, each side of the CML output can be individually

AC coupled and terminated with 50Ω. See Figure 2 for

circuit details.

Figure 1. Simplified Input Interface Schematic

VIN

FILT

BIAS

125Ω

935Ω

IN–

IN+

2.1V

125Ω

6955 F01

Figure 2. Simplified CML Interface Schematic (All OUTx)

VOUT

OUTx–

OUTx+

33Ω

50Ω

6955 F02

The maximum frequency for the input buffer is 7.5GHz, and

the maximum amplitude is 1.6VP-P. It is also important that

the input signal be low noise and have a slew rate of at least

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