LTC6955

16

Rev 0

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

APPLICATIONS INFORMATION

Figure 6. A Typical Data Acquisition Circuit Showing the Sampling Error

Effects of a Noisy Amplifier and a Jittery Sampling Clock

6955 F06

SINE WAVE

INPUT SIGNAL WITH

NOISELESS AMP

SAMPLING CLOCK WITH ADDED JITTER

SINE WAVE

INPUT SIGNAL WITH

NOISY AMP

SINE WAVE

INPUT SIGNAL

PERFECT SAMPLING CLOCK

SINE WAVE

INPUT SIGNAL WITH

NOISELESS AMP

PERFECT SAMPLING CLOCK

SAMPLING CLOCK

BITS

ADC

AMP

ADC Clocking and Jitter Requirements

Adding noise directly to a clean signal clearly reduces its

signal to noise ratio (SNR). In data acquisition applica-

tions, digitizing a clean signal with a noisy clock signal

also degrades the SNR. This issue is best explained in

the time domain using jitter instead of phase noise. For

this discussion, assume that the jitter is white (flat with

frequency) and of Gaussian distribution.

Figure 6 shows a sine wave signal entering a typical data

acquisition circuit composed of an ADC, an input signal

amplifier and a sampling clock. Also shown are three sig-

nal sampling scenarios for sampling the sine wave at its

zero crossing.

In the first scenario, a perfect sine wave input is buffered

by a noiseless amplifier to drive the ADC. Sampling is per-

formed by a perfect, zero jitter clock. Without any added

noise or sampling clock jitter, the ADC’s digitized output

value is very clearly determined and perfectly repeatable

from cycle to cycle.

In the second scenario, a perfect sine wave input is buff-

ered by a noisy amplifier to drive the ADC. Sampling is

performed by a perfect, zero jitter clock. The added noise

results in an uncertainty in the digitized value, causing an

error term which degrades the SNR. The degraded SNR in

this scenario, from adding noise to the signal, is expected.