LTC6955 datasheet(7/22 Pages) AD

7 / 22 page

LTC6955

Rev 0

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

PIN FUNCTIONS

SEL3, SEL2, SEL1, SEL0 (Pins 1, 52, 51, 50): Parallel

Port Control Bits. These CMOS inputs control the output

configuration. See the Operation section for more details.

VD+ (Pin 2): 3.15 to 3.45V Positive Supply Pins for Parallel

Port. This pin should be bypassed directly to the ground

plane using a 0.1µF ceramic capacitor as close to the pin

as possible.

VOUT+ (Pins 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35):

3.15 to 3.45V Positive Supply Pins for Outputs. Each pin

should be separately bypassed directly to the ground

plane using a 0.01µF ceramic capacitor as close to the

pin as possible.

OUT10+, OUT10– (Pins 3, 4): Output Signals. The out-

put is buffered and presented differentially on these pins.

The outputs have 50Ω (typical) output resistance per side

(100Ω differential). The far end of the transmission line

is typically terminated with 100Ω connected across the

outputs. For the LTC6955, this output is an undivided

version of the input, identical to the other outputs. For

the LTC6955-1, only this output is a frequency divided

by two version of the input signal. See the Operation and

Applications Information section for more details.

OUT9+, OUT9– (Pins 6, 7): Output Signals. The output is

buffered and presented differentially on these pins. The

outputs have 50Ω (typical) output resistance per side

(100Ω differential). The far end of the transmission line

is typically terminated with 100Ω connected across the

outputs. This output is an undivided version of the input.

OUT8+, OUT8– (Pins 9, 10): Same as OUT9.

OUT7+, OUT7– (Pins 12, 13): Same as OUT9.

OUT6+, OUT6– (Pins 15, 16): Same as OUT9.

OUT5+, OUT5– (Pins 18, 19): Same as OUT9.

OUT4+, OUT4– (Pins 21, 22): Same as OUT9.

OUT3+, OUT3– (Pins 24, 25): Same as OUT9.

OUT2+, OUT2– (Pins 27, 28): Same as OUT9.

OUT1+, OUT1– (Pins 30, 31): Same as OUT9.

OUT0+, OUT0– (Pins 33, 34): Same as OUT9.

NC (Pin 36): Not Connected Internally. It is recommended

that this pin be connected to the ground pad (Pin 53).

IN+, IN– (Pins 37, 38): Input Signals. The differential

signal placed on these pins is buffered with a low noise

amplifier and fed to the internal distribution path and out-

puts. These self-biased inputs present a differential 250Ω

(typical) resistance to aid impedance matching. They may

be driven single-ended by using the matching circuit in

the Applications Information section.

VIN+ (Pins 39): 3.15 to 3.45V Positive Supply Pin for

Input Circuitry. This pin should be bypassed directly to

the ground plane using a 0.01µF ceramic capacitor as

close to the pin as possible.

FILT (Pin 40): Input Filter Control Pin. When tied to GND,

the input is not filtered. When tied to V+, the input is

filtered to improved noise performance of low slew rate

input signals. See the Operation section for details.

GND (Pin 41): Negative Power Supply (Ground). This pin

should be tied directly to the ground plane with multiple

vias.

NC (Pins 42, 43, 44, 45, 46, 47, 48): No Connect. These

pins should be left open or connected to GND.

TEMP (Pin 49): Temperature Measurement Pin. When

enabled, this outputs a temperature measurement diode

voltage. See the Operation section for details.

GND (Exposed Pad Pin 53): Negative Power Supply

(Ground). The package exposed pad must be soldered

directly to the PCB land. The PCB land pattern should

have multiple thermal vias to the ground plane for both

low ground inductance and also low thermal resistance.

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