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DLPC6421

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DLPS117 – JULY 2018

Product Folder Links: DLPC6421

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Copyright © 2018, Texas Instruments Incorporated

Pin Configurations and Functions (continued)

PIN

(1)

I/O

(2)

DESCRIPTION

NAME

NO.

(8)

GPIO signals must be configured by software for input, output, bidirectional, or open-drain. Some GPIOs have one or more alternate use

modes, which are also software configurable. The reset default for all optional GPIOs is as an input signal. However, any alternate

function connected to these GPIO pins with the exception of general-purpose clocks and PWM generation, are reset. An external pullup

to the 3.3-V supply is required for each signal configured as open-drain. External pullup or pulldown resistors may be required to ensure

stable operation before software is able to configure these ports.

PM_DATA_11

B15

Data Bit (11)

PM_DATA_10

D16

Data Bit (10)

PM_DATA_9

C16

Data Bit (9)

PM_DATA_8

E14

Data Bit (8)

PM_DATA_7

D15

Data Bit (7)

PM_DATA_6

C15

Data Bit (6)

PM_DATA_5

B14

Data Bit (5)

PM_DATA_4

A14

Data Bit (4)

PM_DATA_3

E13

Data Bit (3)

PM_DATA_2

D14

Data Bit (2)

PM_DATA_1

C14

Data Bit (1)

PM_DATA_0

B13

Data Bit (0)

PERIPHERAL INTERFACE

IIC0_SCL

A10

I

an external pull-up to 3.3-V. The minimum acceptable pull-up value is 1 kΩ. This

input is not 5 V tolerant.

IIC0_SDA

B10

2C Bus 0, Data. This bus support 400 kHz, fast mode operation. This signal requires

an external pull-up to 3.3-V. The minimum acceptable pull-up value is 1 kΩ. This

input is not 5 V tolerant.

SSP0_CLK

AD4

Synchronous Serial Port 0, clock

SSP0_RXD

AD5

Synchronous Serial Port 0, receive data in

SSP0_TXD

AB7

Synchronous Serial Port 0, transmit data out

SSP0_CSZ_0

AC5

Synchronous Serial Port 0, chip select 0 (active low)

SSP0_CSZ_1

AB6

Synchronous Serial Port 0, chip select 1 (active low)

SSP0_CSZ_2

AC3

Synchronous Serial Port 0, chip select 2 (active low)

UART0_TXD

AB3

UART0 transmit data output

UART0_RXD

AD1

UART0 receive data input

UART0_RTSZ

AD2

UART0 ready to send hardware flow control output (active low)

UART0_CTSZ

AE2

UART0 clear to send hardware flow control input (active low)

USB_DAT_N

C5

USB D- I/O

USB_DAT_P

D6

USB D+ I/O

PMD_INTZ

AE8

This signal requires an external pull-up. Uses hysteresis.

CW_PWM

AD8

Reserved

CW_INDEX

AF7

Reserved

LMPCTRL

AC9

Reserved

LMPSTAT

AF8

Reserved

GENERAL PURPOSE I/O (GPIO)

(8)

Software Function 1

Alternate Software Function 2

GPIO_82

E3

N/A

N/A

GPIO_81

AB10

N/A

N/A

GPIO_80

AD9

N/A

N/A

GPIO_79

AE9

HEARTBEAT(O)

N/A

GPIO_78

AF9

FIELD_3D_LR (I)

N/A

GPIO_77

AB11

SAS_INTGTR_EN (O)

N/A

GPIO_76

AC10

SAS_CSZ (O)

N/A

GPIO_75

AD10

SAS_DO (O)

SENSE_FREQ_IN (I)

GPIO_74

AE10

SAS_DI (I)

N/A

GPIO_73

AF10

SAS_CLK (O)

N/A

GPIO_72

K24

SSP2_DI (I)

N/A

GPIO_71

K23

SSP2_CLK (B)

N/A

GPIO_70

K22

SSP2_CSZ_1 (B)

N/A

GPIO_69

J26

SSP2_CSZ_0 (B)

N/A

GPIO_68

J25

SSP2_DO (O)

N/A