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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DLPC6421 датащи(PDF) 21 Page - Texas Instruments |
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DLPC6421 датащи(HTML) 21 Page - Texas Instruments |
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21 / 48 page  21 DLPC6421 www.ti.com DLPS117 – JULY 2018 Product Folder Links: DLPC6421 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated (1) The minimum cycle time (tc) for DCK_A and DCL_B includes 1.0% spread spectrum modulation. User must verify that DMD can support this rate. (2) Output Setup & Hold times for DMD clock frequencies below the maximum can be calculated as follows: tosu(fclock) = tosu(fmax) + 250000*(1/fclock – 1/400) & toh(fclock) = toh(fmax) + 250000*(1/fclock – 1/400) where fclock is in MHz. 6.10 DMD LVDS Interface Timing Requirements Parameter FROM (INPUT) TO (OUTPUT) MIN MAX UNIT fclock Clock frequency, DCK_A N/A DCK_A 100 400 MHz tC Cycle time, DCK_A(1) N/A DCK_A 2475.3 ps tW(H) Pulse duration, high N/A DCK_A 1093 ps tW(L) Pulse duration, low N/A DCK_A 1093 ps tt Transition time, tt= tf/tr N/A DCK_A 100 400 ps tosu Output Setup time at max clock rate(2) DCK_A ↑↓ SCA, DDA(15:0) 438 ps toh Output hold time at max clock rate(2) DCK_A ↑↓ SCA, DDA(15:0) 438 ps fclock Clock frequency, DCK_B N/A DCK_B 100 400 MHz tC Cycle time, DCK_B(1) N/A DCK_B 2475.3 ps tW(H) Pulse duration, high N/A DCK_B 1093 ps tW(L) Pulse duration, low N/A DCK_B 1093 ps tt Transition time, tt= tf/tr N/A DCK_B 100 400 ps tosu Output Setup time at max clock rate (2) DCK_B ↑↓ SCA, DDB(15:0) 438 ps toh Output hold time at max clock rate(2) DCK_B ↑↓ SCA, DDB(15:0) 438 ps tsk Output Skew, Channel A to Channel B DCK_A ↑ DCK_B ↑ 250 ps 6.11 Synchronous Serial Port (SSP) Interface Timing Requirements PARAMETER TEST CONDITIONS MIN MAX UNIT SSP MASTER tsu Setup time, SSPx_DI valid before SSPx_CLK 15 ns tsu Setup time, SSPx_DI valid before SSPx_CLK 15 ns th Hold time, SSPx_DI valid after SSPx_CLK 0 ns th Hold time, SSPx_DI valid after SSPx_CLK 0 ns t t Transition time, SSPx_DI, tt= tf/tr 20% to 80% reference points (signal) 1.5 ns SSP SLAVE tsu Setup time, SSPx_DI valid before SSPx_CLK 12 ns tsu Setup time, SSPx_DI valid before SSPx_CLK 12 ns th Hold time, SSPx_DI valid after SSPx_CLK 12 ns th Hold time, SSPx_DI valid after SSPx_CLK 12 ns t t Transition time, SSPx_DI, tt= tf/tr 20% to 80% reference points (signal) 1.5 ns |
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