DLPC6421 datasheet(4/48 Pages) TI1

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DLPC6421

DLPS117 – JULY 2018

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Product Folder Links: DLPC6421

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(1)

For instructions on handling unused pins, see General Handling Guidelines for Unused CMOS-type Pins.

(2)

I/O Type: I = Input, O = Output, B = Bidirectional, and H = Hysteresis. See Table 1 for subscript explanation.

(3)

All JTAG signals are LVTTL compatible.

Pin Configurations and Functions

(1)

I/O

(2)

DESCRIPTION

NAME

NO.

POSENSE

P22

Power-On Sense, High true, signal provided from an external voltage monitor circuit.

This signal should be driven active (high) when all DLPC6421 supply voltages have

reached 90% of their specified minimum voltage. This signal should be driven

inactive (low) after the falling edge of PWRGOOD as specified.

PWRGOOD

T26

Power Good, High true, signal from external power supply or voltage monitor. A high

value indicates all power is within operating voltage specs and the system is safe to

exit its reset state. A transition from high to low is used to indicate that the controller

or DMD supply voltage will drop below their rated minimum level. This transition must

occur prior to the supply voltage drop as specified. During this interval, POSENSE

must remain active high. This is an early warning of an imminent power loss

condition. This warning is required to enhance long term DMD reliability. A DMD park

followed by a full controller reset is performed by the DLPC6421 controller when

PWRGOOD goes low for the specified minimum, protecting the DMD. This minimum

de-assertion time is used to protect the input from glitches. Following this the

DLPC6421 controller will be held in its reset state as long as PWRGOOD is low.

PWRGOOD must be driven high for normal operation. The DLPC6421 controller will

acknowledge PWRGOOD as active once it’s been driven high for it’s specified

minimum time. Uses hysteresis.

EXT_ARTZ

T24

General purpose, LOW true, reset output. This output is asserted low immediately

upon asserting power-up reset (POSENSE) low and remains low while POSENSE

remains low. EXT_ARSTZ continues to be held low after the release of power-up

reset (that is, POSENSE set high) until released by software. EXT_ARSTZ is also

asserted low approximately 5 µs after the detection of a PWRGOOD or any internally

generated reset. In all cases it will remain active for a minimum of 2 ms. Note that the

DLPC6421 contains a software register that can be used to independently drive this

output.

MTR_ARTZ

T25

Reserved

BOARD LEVEL TEST AND INITIALIZATION

(3)

TDI

N25

JTAG serial data in

TCK

N24

JTAG serial data clock

TMS1

P25

JTAG test mode select

TMS2

P26

JTAG test mode select

TDO1

N23

JTAG serial data out

TDO2

N22

JTAG serial data out

TRSTZ

M23

JTAG reset. This signal includes an internal pull-up and utilizes hysteresis. This pin

should be pulled high (or left unconnected) when the JTAG interface is in use for

boundary scan or ARM debug. Connect this pin to ground otherwise. Failure to tie

this pin low during normal operation will cause startup and initialization problems.

RTCK

JTAG return clock

ETM_PIPESTAT_2

ETM trace port pipeline status. Indicates the pipeline status of the ARM core. These

signals include internal pull-downs.

ETM_PIPESTAT_1

ETM_PIPESTAT_0

ETM_TRACESYNC

ETM trace port synchronization signal, indicating the start of a branch sequence on

the trace packet port. This signal includes an internal pull-down.

ETM_TRACECLK

ETM trace port clock. This signal includes an internal pull-down.

ICTSEN

M24

IC tri-State enable (active high). Asserting high will tri-state all outputs except the

JTAG interface. This signal includes an internal pull-down however TI recommends

an external pull-down for added protection. Uses hysteresis.

TSTPT_7

Test pin 7 - This signal provides internal pull-downs.