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DLPC6421

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DLPS117 – JULY 2018

Product Folder Links: DLPC6421

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Copyright © 2018, Texas Instruments Incorporated

Pin Configurations and Functions (continued)

PIN

(1)

I/O

(2)

DESCRIPTION

NAME

NO.

(4)

Ports 1 and 2 can each be used to support multiple source options for a given product. To do so, the data bus from both source

components must be connected to the same port pins (1 or 2) and control given to the DLPC6421 device to tri-state the "inactive"

source. Tying them together like this will cause some signal degradation due to reflections on the tri-stated path. Given the clock is the

most critical signal, Port clocks (1 and 2) are provided to provide an option to improve the signal integrity.

(5)

Ports 1 and 2 can be combined into one 60-bit port (typically for high data rate sources) for transmission of two pixels per clock.

(6)

The A, B, C input data channels of Ports 1 and 2 can be internally re-configured/ re-mapped for optimum board layout.

(7)

Sources feeding less than the full 10-bits per color component channel should be MSB justified when connected to the DLPC6421

controller and the LSBs tied off to zero. For example an 8-bit per color input should be connected to bits 9:2 of the corresponding A, B,

C input channel.

TSTPT_1

D3

Test pin 1 - This signal provides internal pull-downs. Additionally, TI recommends

that jumper options be provided for connecting TSTPT(2:0) to external pull-ups.

TSTPT_0

C2

Test pin 0 - This signal provides internal pull-downs. Additionally, TI recommends

that jumper options be provided for connecting TSTPT(2:0) to external pull-ups.

DEVICE TEST

HW_TEST_EN

M25

Device manufacturing test enable; This signal includes an internal pull-down and

utilizes hysteresis. TI recommends that this signal be tied to an external ground in

normal operation for added protection.

ANALOG FRONT END

AFE_ARSTZ

AC12

Reserved

AFE_CLK

AD12

Reserved

AFE_IRQ

AB13

Reserved

PORT1 and PORT 2 CHANNEL DATA and CONTROL

(4) (5) (6) (7)

P_CLK1

AE22

Input port data pixel write clock (selectable as rising or falling edge triggered, and

which port it is associated with (A or B or (A and B))). This signal includes an internal

pull-down.

P_CLK2

W25

Input port data pixel write clock (selectable as rising or falling edge triggered, and

which port it is associated with (A or B or (A and B))). This signal includes an internal

pull-down.

P_CLK3

AF23

Input port data pixel write clock (selectable as rising or falling edge triggered, and

which port it is associated with (A or B or (A and B))). This signal includes an internal

pull-down.

P_DATAEN1

AF22

Active high data enable. Selectable as to which port it is associated with (A or B or (A

and B)).This signal includes an internal pull-down.

P_DATAEN2

W24

Active high data enable. Selectable as to which port it is associated with (A or B or (A

and B)).This signal includes an internal pull-down.

P1_A_9

AD15

Port 1 A Channel Input Pixel Data (bit weight 128)

P1_A_8

AE15

Port 1 A Channel Input Pixel Data (bit weight 64)

P1_A_7

AE14

Port 1 A Channel Input Pixel Data (bit weight 32)

P1_A_6

AE13

Port 1 A Channel Input Pixel Data (bit weight 16)

P1_A_5

AD13

Port 1 A Channel Input Pixel Data (bit weight 8)

P1_A_4

AC13

Port 1 A Channel Input Pixel Data (bit weight 4)

P1_A_3

AF14

Port 1 A Channel Input Pixel Data (bit weight 2)

P1_A_2

AF13

Port 1 A Channel Input Pixel Data (bit weight 1)

P1_A_1

AF12

Port 1 A Channel Input Pixel Data (bit weight 0.5)

P1_A_0

AE12

Port 1 A Channel Input Pixel Data (bit weight 0.25)

P1_B_9

AF18

Port 1 B Channel Input Pixel Data (bit weight 128)

P1_B_8

AB18

Port 1 B Channel Input Pixel Data (bit weight 64)

P1_B_7

AC15

Port 1 B Channel Input Pixel Data (bit weight 32)

P1_B_6

AC16

Port 1 B Channel Input Pixel Data (bit weight 16)

P1_B_5

AD16

Port 1 B Channel Input Pixel Data (bit weight 8)

P1_B_4

AE16

Port 1 B Channel Input Pixel Data (bit weight 4)

P1_B_3

AF16

Port 1 B Channel Input Pixel Data (bit weight 2)

P1_B_2

AF15

Port 1 B Channel Input Pixel Data (bit weight 1)

P1_B_1

AC14

Port 1 B Channel Input Pixel Data (bit weight 0.5)

P1_B_0

AD14

Port 1 B Channel Input Pixel Data (bit weight 0.25)

P1_C_9

AD20

Port 1 C Channel Input Pixel Data (bit weight 128)

P1_C_8

AE20

Port 1 C Channel Input Pixel Data (bit weight 64)

P1_C_7

AE21

Port 1 C Channel Input Pixel Data (bit weight 32)

P1_C_6

AF21

Port 1 C Channel Input Pixel Data (bit weight 16)

P1_C_5

AD19

Port 1 C Channel Input Pixel Data (bit weight 8)

P1_C_4

AE19

Port 1 C Channel Input Pixel Data (bit weight 4)