DLPC6421 datasheet(6/48 Pages) TI1

6 / 48 page

DLPC6421

DLPS117 – JULY 2018

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Product Folder Links: DLPC6421

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Pin Configurations and Functions (continued)

(1)

I/O

(2)

DESCRIPTION

NAME

NO.

P1_C_3

AF19

Port 1 C Channel Input Pixel Data (bit weight 2)

P1_C_2

AF20

Port 1 C Channel Input Pixel Data (bit weight 1)

P1_C_1

AC19

Port 1 C Channel Input Pixel Data (bit weight 0.5)

P1_C_0

AE19

Port 1 C Channel Input Pixel Data (bit weight 0.25)

P1_VSYNC

AC20

Port 1 Vertical Sync. This signal includes an internal pull-down. While intended to be

associated with Port 1, it can be programmed for use with Port 2.

P1_HSYNC

AD21

Port 1 Horizontal Sync. This signal includes an internal pull-down. While intended to

be associated with Port 1, it can be programmed for use with Port 2.

P2_A_9

AD26

Port 2 A Channel Input Pixel Data (bit weight 128)

P2_A_8

AD25

Port 2 A Channel Input Pixel Data (bit weight 64)

P2_A_7

AB21

Port 2 A Channel Input Pixel Data (bit weight 32)

P2_A_6

AC22

Port 2 A Channel Input Pixel Data (bit weight 16)

P2_A_5

AD23

Port 1 A Channel Input Pixel Data (bit weight 8)

P2_A_4

AB20

Port 2 A Channel Input Pixel Data (bit weight 4)

P2_A_3

AC21

Port 2 A Channel Input Pixel Data (bit weight 2)

P2_A_2

AD22

Port 2 A Channel Input Pixel Data (bit weight 1)

P2_A_1

AE23

Port 2 A Channel Input Pixel Data (bit weight 0.5)

P2_A_0

AB19

Port 2 A Channel Input Pixel Data (bit weight 0.25)

P2_B_9

Y22

Port 2 B Channel Input Pixel Data (bit weight 128)

P2_B_8

AB26

Port 2 B Channel Input Pixel Data (bit weight 64)

P2_B_7

AA23

Port 2 B Channel Input Pixel Data (bit weight 32)

P2_B_6

AB25

Port 2 B Channel Input Pixel Data (bit weight 16)

P2_B_5

AA22

Port 2 B Channel Input Pixel Data (bit weight 8)

P2_B_4

AB24

Port 2 B Channel Input Pixel Data (bit weight 4)

P2_B_3

AC26

Port 2 B Channel Input Pixel Data (bit weight 2)

P2_B_2

AB23

Port 2 B Channel Input Pixel Data (bit weight 1)

P2_B_1

AC25

Port 2 B Channel Input Pixel Data (bit weight 0.5)

P2_B_0

AC24

Port 2 B Channel Input Pixel Data (bit weight 0.25)

P2_C_9

W23

Port 2 C Channel Input Pixel Data (bit weight 128)

P2_C_8

V22

Port 2 B Channel Input Pixel Data (bit weight 64)

P2_C_7

Y26

Port 2 C Channel Input Pixel Data (bit weight 32)

P2_C_6

Y25

Port 2 B Channel Input Pixel Data (bit weight 16)

P2_C_5

Y24

Port 2 C Channel Input Pixel Data (bit weight 8)

P2_C_4

Y23

Port 2 B Channel Input Pixel Data (bit weight 4)

P2_C_3

W22

Port 2 C Channel Input Pixel Data (bit weight 2)

P2_C_2

AA26

Port 2 B Channel Input Pixel Data (bit weight 1)

P2_C_1

AA25

Port 2 C Channel Input Pixel Data (bit weight 0.5)

P2_C_0

AA24

Port 2 B Channel Input Pixel Data (bit weight 0.25)

P2_VSYNC

U22

Port 2 Vertical Sync. This signal includes an internal pull-down. While intended to be

associated with Port 2, it can be programmed for use with Port1.

P2_HSYNC

W26

Port 2 Horizontal Sync. This signal includes an internal pull-down. While intended to

be associated with Port 2, it can be programmed for use with Port1.

ALF INPUT PORT CONTROL

ALF_VSYNC

AF11

Reserved

ALF_HSYNC

AD11

Reserved

ALF_CSYNC

AE11

Reserved

DMD RESET and BIAS CONTROL

DADOEZ

AE7

Reserved

DADADDR_3

AD6

Reserved

DADADDR_2

AE5

DADADDR_1

AF4

DADADDR_0

AB8

DADMODE_1

AD7

Reserved

DADMODE_0

AE6

DADSEL_1

AE4

Reserved

DADSEL_0

AC7

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