DLPC6421 datasheet(26/48 Pages) TI1

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DLPC6421

DLPS117 – JULY 2018

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7 Detailed Description

7.1 Overview

As with prior DLP® electronics solutions, image data is 100% digital from the DLPC6421 input port to the image

projected on to the display screen. The image stays in digital form and is never converted into an analog signal.

The DLPC6421 processes the digital input image and converts the data into bit-plane format as needed by the

DMD. The DLPC6421 display controller is optimized for high-resolution and high-brightness display applications.

Applications include 4K UHD display applications, mobile smart tv, smart home displays, and digital signage.

7.2 Feature Description

7.2.1 System Reset Operation

7.2.1.1 Power-up Reset Operation

Immediately following a power-up event, DLPC6421 hardware automatically brings up the Master PLL and

places the DLPC6421 in normal power mode. It then follows the standard system reset procedure (see System

Reset Operation).

7.2.1.2 System Reset Operation

Immediately following any type of system reset (Power-up reset, PWRGOOD reset, watchdog timer timeout,

MTR_RSTZ reset, etc), the DLPC6421 device shall automatically return to NORMAL power mode and return to

the following state:

•

All GPIO will tri-state.

•

The Master PLL will remain active (it is reset only after a power-up reset sequence) and most of the derived

clocks are active. However, only those resets associated with the ARM9 processor and its peripherals will be

released (The ARM9 is responsible for releasing all other resets).

•

ARM9 associated clocks default to their full clock rates, boot-up is at full speed.

•

All front end derived clocks are disabled.

•

The PLL feeding the LVDS DMD I/F (PLLD) defaults to its power-down mode and all derived clocks are

inactive with corresponding resets asserted (The ARM9 is responsible for enabling these clocks and releasing

associated resets).

•

LVDS I/O defaults to its power-down mode with outputs tri-stated.

•

All resets output by the DLPC6421 device remain asserted until released by the ARM9 after boot-up.

•

The ARM9 processor boots-up from external flash.

When the ARM9 boots-up, the ARM9 API:

•

Configures the programmable DDR Clock Generator (DCG) clock rates (i.e. the DMD LVDS I/F rate)

•

Enables the DCG PLL (PLLD) while holding divider logic in reset

•

When the DCG PLL locks, ARM9 software sets DMD clock rates

•

API software then releases DCG divider logic resets, which in turn, enable all derived DCG clocks

•

Release external resets

Application software then typically waits for a wake-up command through software or through PROJ_ON pin from

the end user. When the projector is requested to wake-up, the software places the DLPC6421 back in normal

mode, re-initialize clocks, and resets as required.

7.2.2 Spread Spectrum Clock Generator Support

The DLPC6421 controller supports limited, internally-controlled, spread spectrum clock spreading on the DMD

interface. The purpose of this is to frequency spread all signals on this high-speed, external interface to reduce

EMI emissions. Clock spreading is limited to triangular waveforms. The DLPC6421 controller provides

modulation options of 0%, +/-0.5% and +/-1.0% (center-spread modulation).

DLPC6421 датащи(PDF) 26 Page - Texas Instruments

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