P89LPC907FD datasheet(28/51 Pages) PHILIPS

28 / 51 page

Philips Semiconductors

P89LPC906/907/908

8-bit microcontrollers with two-clock 80C51 core

Product data

Rev. 05 — 17 December 2004

28 of 51

9397 750 14467

The P89LPC906 supports 6 interrupt sources: timers 0 and 1, brownout detect,

watchdog/real-time clock, keyboard, and the comparator.

The P89LPC907 supports 8 interrupt sources: timers 0 and 1, serial port Tx,

combined serial port Rx/Tx (no Rx function is available on this device), brownout

detect, watchdog/real-time clock, keyboard, and the comparator.

The P89LPC908 supports 9 interrupt sources: timers 0 and 1, serial port Tx, serial

port Rx, combined serial port Rx/Tx, brownout detect, watchdog/real-time clock,

keyboard, and the comparator.

Each interrupt source can be individually enabled or disabled by setting or clearing a

bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a

global disable bit, EA, which disables all interrupts.

Each interrupt source can be individually programmed to one of four priority levels by

setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An

interrupt service routine in progress can be interrupted by a higher priority interrupt,

but not by another interrupt of the same or lower priority. The highest priority interrupt

service cannot be interrupted by any other interrupt source. If two requests of

different priority levels are pending at the start of an instruction, the request of higher

priority level is serviced.

If requests of the same priority level are pending at the start of an instruction, an

internal polling sequence determines which request is serviced. This is called the

arbitration ranking. Note that the arbitration ranking is only used to resolve pending

requests of the same priority level.

8.10.1

External interrupt inputs

The P89LPC906/907/908 has a Keypad Interrupt function. This can be used as an

external interrupt input.

If enabled when the P89LPC906/907/908 is put into Power-down or Idle mode, the

interrupt will cause the processor to wake-up and resume operation. Refer to Section

8.13 “Power reduction modes” for details.

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