P89LPC907FD datasheet(25/51 Pages) PHILIPS

25 / 51 page

Philips Semiconductors

P89LPC906/907/908

8-bit microcontrollers with two-clock 80C51 core

Product data

Rev. 05 — 17 December 2004

25 of 51

9397 750 14467

external circuit is required to hold the device in reset at power-up until VDD has

reached its speciﬁed level. When system power is removed VDD will fall below

the minimum speciﬁed operating voltage. When using an oscillator frequency

above 12 MHz, in some applications, an external brownout detect circuit may

be required to hold the device in reset when VDD falls below the minimum

speciﬁed operating voltage. If CCLK is 8 MHz or slower, the CLKLP SFR bit

(AUXR1.7) can be set to ‘1’ to reduce power consumption. On reset, CLKLP is ‘0’

allowing highest performance access. This bit can then be set in software if CCLK is

running at 8 MHz or slower.

8.2.6

Clock output (P89LPC906)

The P89LPC906 supports a user selectable clock output function on the

XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if

another clock source has been selected (on-chip RC oscillator, Watchdog oscillator,

external clock input on X1) and if the Real-Time clock is not using the crystal

oscillator as its clock source. This allows external devices to synchronize to the

P89LPC906. This output is enabled by the ENCLK bit in the TRIM register. The

frequency of this clock output is 1

⁄

2 that of the CCLK. If the clock output is not needed

in Idle mode, it may be turned off prior to entering Idle, saving additional power.

8.3 On-chip RC oscillator option

The P89LPC906/907/908 has a 6-bit TRIM register that can be used to tune the

frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory

pre-programmed value to adjust the oscillator frequency to 7.373 MHz,

±2.5 %.

End-user applications can write to the Trim register to adjust the on-chip RC oscillator

to other frequencies. If CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can

be set to ‘1’ to reduce power consumption. On reset, CLKLP is ‘0’ allowing highest

performance access. This bit can then be set in software if CCLK is running at 8 MHz

or slower.

8.4 Watchdog oscillator option

The watchdog has a separate oscillator which has a frequency of 400 kHz. This

oscillator can be used to save power when a high clock frequency is not needed.

8.5 External clock input option (P89LPC906)

In this conﬁguration, the processor clock is derived from an external source driving

the XTAL1/P3.1 pin. The rate may be from 0 Hz up to 18 MHz. The XTAL2/P3.0 pin

may be used as a standard port pin or a clock output. When using an oscillator

frequency above 12 MHz, the reset input function of P1.5 must be enabled. An

external circuit is required to hold the device in reset at power-up until VDD has

reached its speciﬁed level. When system power is removed VDD will fall below

the minimum speciﬁed operating voltage. When using an oscillator frequency

above 12 MHz, in some applications, an external brownout detect circuit may

be required to hold the device in reset when VDD falls below the minimum

speciﬁed operating voltage.

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