TCLK1, TCLK2 : Transmit Clock (Pins 4, 45)

TPOS1, TPOS2 : Transmit Positive Data (Pins 5, 44)

TNEG1, TNEG2 : Transmit Negative Data (Pins 6, 43)

The transmit clock and data are input on these pins. The signal is driven to the line at TTIP and

TRING. Data on TPOS and TNEG are sampled on the falling edge of TCLK. An input on

TPOS causes a positive pulse to be transmitted at TTIP and TRING, while an input on TNEG

input causes a negative pulse to be transmitted at TTIP and TRING.

Oscillator

1XCLK : One-times Clock Frequency Select (Pin 28)

When 1XCLK is set high, REFCLK must be a 1X clock (i.e., 1.544 MHz for T1 applications or

2.048 MHz for E1 applications). When 1XCLK is set low, REFCLK must be an 8X clock (i.e.,

12.352 MHz for T1 applications or 16.384 MHz for E1 applications).

REFCLK : External Reference Clock Input (Pin 26)

Input reference clock for the receive and jitter attenuator circuits. When 1XCLK is set high,

REFCLK must be a 1X clock (i.e., 1.544 MHz

±100 ppm for T1 applications or 2.048 MHz

±100 ppm for E1 applications). When 1XCLK is set low, REFCLK must be an 8X clock (i.e.,

12.352 MHz

±100 ppm for T1 applications or 16.384 MHz ±100 ppm for E1 applications). The

REFCLK input also determines the transmission rate when TAOS is asserted.

Control

CLKE : Clock Edge (Pin 41)

Controls the polarity of the recovered clock RCLK. When CLKE is high, RPOS and RNEG are

valid on the falling edge of RCLK. When CLKE is low, RPOS and RNEG are valid on the

rising edge of RCLK.

CON01, CON11, CON21 : Configuration for Channel 1 (Pins 58, 53, 51)

CON02, CON12, CON22 : Configuration for Channel 2 (Pins 54, 52, 50)

These pins configure the transmitter (pulse shape, pulse width, pulse amplitude, and driver

impedance) and receiver (slicing level). The CONx1 pins control channel 1 and the CONx2

pins control channel 2. Both channels must be configured to operate at the same data rate on

the line interface (both T1 or both E1).

LLOOP1, LLOOP2 : Local Loopback (Pins 62, 61)

A local loopback is enabled when LLOOP is high. During local loopback, the TCLK, TPOS,

and TNEG inputs are looped back through the jitter attenuator to the RCLK, RPOS, and RNEG

outputs. The data at TPOS and TNEG continues to be transmitted to the line interface unless

overridden by a TAOS request. The inputs at RTIP and RRING are ignored.

RESET : Reset (Pin 25)

A device reset is selected by setting the RESET pin high for a minimum of 200 ns. The reset

function initiates on the falling edge of RESET and requires less than 20 ms to complete. The

control logic is initialized and LOS is set high.

DS224PP1

23