CS61582 datasheet(14/32 Pages) CIRRUS

14 / 32 page

shift operation. Note that if J-TDI is floating,

an internal pull-up resistor forces the pin high.

JTAG Data Registers (DR)

The test data registers are the Boundary-Scan

ter (DIR), and the Bypass Register (BR).

Boundary Scan Register: The BSR is connected

in parallel to all the digital I/O pins, and pro-

vides the mechanism for applying/reading test

patterns to/from the board traces. The BSR is 65

bits long and is initialized and read using the in-

struction SAMPLE/PRELOAD. The bit ordering

for the BSR is the same as the top-view package

pin out, beginning with the LOS1 pin and mov-

ing counter-clockwise to end with the RLOOP2

pin as shown in Table 3.

The input pins require one bit in the BSR and

only one J-TCK cycle is required to load test

data for each input pin.

The output pins have two bits in the BSR to de-

fine output high, output low, or high impedance.

The first bit (shifted in first) selects between an

output-enabled state (bit set to 1) or high-imped-

ance state (bit set to 0). The second bit shifted in

contains the test data that may be output on the

pin. Therefore, two J-TCK cycles are required to

load test data for each output pin.

The bi-directional pins have three bits in the

BSR to define input, output high, output low, or

high impedance. The first bit shifted into the

BSR configures the output driver as high-imped-

ance (bit set to 0) or active (bit set to 1). The

second bit shifted into the BSR sets the output

value when the first bit is 1. The third bit cap-

tures the value of the pin. This pin may have its

value set externally as an input (if the first bit is

0) or set internally as an output (if the first bit is

1). To configure a pad as an input, the J-TDI

pattern is 0X0. To configure a pad as an output,

the J-TDI pattern is 1X1. Therefore, three J-TCK

cycles are required to load test data for each bi-

directional pin.

Device Identification Register: The DIR provides

the manufacturer, part number, and version of the

CS61582. This information can be used to verify

that the proper version or revision number has

been used in the system under test. The DIR is 32

bits long and is partitioned as shown in figure 10.

BSR bits

Pin Name

Pad Type

0-2

LOS1

bi-directional

3-5

TNEG1

bi-directional

TPOS1

input

TCLK1

input

8-9

RNEG1

output

10-11

RPOS1

output

12-13

RCLK1

output

14-16

DPM1

bi-directional

17-19

RLOOP1

bi-directional

LLOOP2

input

21-23

LLOOP1

bi-directional

24-26

TAOS1

bi-directional

27-29

TAOS2

bi-directional

30-32

CON01

bi-directional

33-35

CON02

bi-directional

36-38

CON11

bi-directional

39-41

CON12

bi-directional

42-44

CON21

bi-directional

CON22

input

46-48

DPM2

bi-directional

49-50

RCLK2

output

51-52

RPOS2

output

53-54

RNEG2

output

TCLK2

input

TPOS2

input

57-59

TNEG2

bi-directional

60-62

LOS2

bi-directional

CLKE

input

RLOOP2

input

1. Configure pad as an input.

2. Configure pad as an output.

Table 3. Boundary Scan Register

DS224PP1

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