pins within

±5% of nominal; Inputs: Logic 0 = 0V, Logic 1 = DV+) (See Figures 1, 2, and 3)

Parameter

Symbol

Min

Typ

Max

Units

TCLK Frequency

(Note 25)

-

1.544

-

MHz

TCLK Duty Cycle

30

50

70

%

RCLK Duty Cycle

45

50

55

%

Rise Time (All Digital Outputs)

(Note 26)

-

-

65

ns

Fall Time (All Digital Outputs)

(Note 26)

-

-

65

ns

RPOS/RNEG to RCLK Rising Setup Time

-

274

-

ns

RCLK Rising to RPOS/RNEG Hold Time

-

274

-

ns

TPOS/TNEG to TCLK Falling Setup Time

25

-

-

ns

TCLK Falling to TPOS/TNEG Hold Time

25

-

-

ns

Notes: 25. The maximum burst rate of a gapped TCLK input clock is 8.192 MHz. The maximum gap size

that can be tolerated on TCLK is 28 UIp-p.

26. At max load of 50 pF.

pins within

±5% of nominal; Inputs: Logic 0 = 0V, Logic 1 = DV+) (See Figures 1, 2, and 3)

Parameter

Symbol

Min

Typ

Max

Units

TCLK Frequency

(Note 25)

-

2.048

-

MHz

TCLK Duty Cycle

30

50

70

%

RCLK Duty Cycle

45

50

55

%

Rise Time (All Digital Outputs)

(Note 26)

-

-

65

ns

Fall Time (All Digital Outputs)

(Note 26)

-

-

65

ns

RPOS/RNEG to RCLK Rising Setup Time

-

194

-

ns

RCLK Rising to RPOS/RNEG Hold Time

-

194

-

ns

TPOS/TNEG to TCLK Falling Setup Time

25

-

-

ns

TCLK Falling to TPOS/TNEG Hold Time

25

-

-

ns

6

DS224PP1