ISL97635A datasheet(20/29 Pages) RENESAS

20 / 29 page

ISL97635A

FN6564 Rev.3.00

Page 20 of 29

Sep 26, 2017

The PWM_SEL bit determines whether the SMBus or PWMI input

should drive the output brightness in terms of PWM dimming.

When PWM_SEL bit is 1, the PWMI drives the output brightness

regardless of what the PWM_MD is.

When the PWM_SEL bit is 0, the PWM_MD bit selects the

manner in which the PWM dimming is to be interpreted; when

this bit is 1, the PWM dimming is based on the SMBus brightness

setting. When this bit is 0, the PWM dimming reflects a

percentage change in the current brightness programmed in the

SMBus register 0x00, i.e. DPST (Display Power Saving

Technology) mode as shown in Equation 15:

where:

Cbt = Current brightness setting from SMBus register 0x00 without

influence from the PWMI

PWMI = is the percent duty cycle of the PWMI

For example, the Cbt = 50% duty cycle programmed in the SMBus

appropriate capacitor at the FPWM pin. On the other hand, PWMI is

fed with a 1kHz 30% high PWM signal. When PWM_SEL = 0 and

PWM_MD = 0, the device is in DPST operation where DPST

brightness = 15% PWM dimming at 200Hz.

• All reserved bits return a “0” when read.

• All reserved bits have no functional effect when written.

• All defined control bits return their current, latched value when

read.

• A value of 1 written to BL_CTL turns on the BL in 4ms or less after

the write cycle completes. The BL is deemed to be on when Bit 3

BL_STAT of register 0x02 is 1 and register 0x09 is not 0. See

Figures 24 and 25.

• A value of 0 written to BL_CTL immediately turns off the BL.

The BL is deemed to be off when Bit 3 BL_STAT of register

0x02 is 0 and register 0x09 is 0. See Figures 24 and 25.

• ** Note that the behavior of register 0x00 (Brightness Control

bits, as shown in Table 3 “Operating Modes Selected by Device

Control Register Bits 1 and 2.”

• When an SMBus mode is selected, register 0x00 reflects the

last value written to it. But, when any non-SMBus mode is

selected, register 0x00 reflects the current brightness value

based on the current mode of operation, with the exception of

SMBus mode with DPST, where PWM_MD = 0 and

PWM_SEL = 0.

FIGURE 24. DESCRIPTIONS OF BRIGHTNESS CONTROL REGISTER

PWM BRIGHTNESS CONTROL REGISTER

BRT7

BRT6

BRT5

BRT4

BRT3

BRT2

BRT1

BRT0

Bit 7 (R/W)

Bit 6 (R/W)

Bit 5 (R/W)

Bit 4 (R/W)

Bit 3 (R/W)

Bit 2 (R/W)

Bit 1 (R/W)

Bit 0 (R/W)

BIT ASSIGNMENT

BIT FIELD DEFINITIONS

BRT[7..0]

= 256 steps of PWM brightness levels

FIGURE 25. DESCRIPTIONS OF DEVICE CONTROL REGISTER

DEVICE CONTROL REGISTER

RESERVED

PWM_MD

PWM_SEL

BL_CTL

Bit 7 (R/W)

Bit 6 (R/W)

Bit 5 (R/W)

Bit 4 (R/W)

Bit 3 (R/W)

Bit 2 (R/W)

Bit 1 (R/W)

Bit 0 (R/W)

BIT ASSIGNMENT

BIT FIELD DEFINITIONS

PWM_MD

= PWM mode select bit (1 = absolute brightness, 0 =

% change) default = 0

PWM_SEL

= Brightness control select bit (1 = control by PWMI,

0 = control by SMBus) default = 0

BL_CTL

= BL On/Off (1 = On, 0 = Off) default = 0

DPST Brightness

Cbt PWMI



(EQ. 15)

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