ISL97635A datasheet(15/29 Pages) RENESAS

15 / 29 page

ISL97635A

FN6564 Rev.3.00

Page 15 of 29

Sep 26, 2017

For the extensive fault protection conditions, please refer to

Figure 19 and Table 1 for details.

FIGURE 19. SIMPLIFIED FAULT PROTECTIONS

VSC

IIN5

VSET

DC CURRENT

PWM/OC0/SC0

REF

FET

DRIVER

IMAX

ILIMIT

DRIVER

FAULT

OVP

VIN

OTP

THRM

SHDN

VSC

IIN0

VOUT

SMBUS

CONTROL

LOGIC

FAULT/

STATUS

VSET

PWM/OC5/SC5

TEMP

SENSOR

LOGIC

OTP

THRM

SHDN

O/P

SHORT

REG

VSET/2

TABLE 1. PROTECTIONS TABLE

CASE

FAILURE MODE

DETECTION MODE

FAILED CHANNEL ACTION

GOOD CHANNELS ACTION

VOUT REGULATED BY

CH0 Short-Circuit

Upper

Over-Temperature

Protection limit

(OTP) not triggered

and VIIN0 < VSC

CH0 ON and burns power

CH1 through CH5 Normal

Highest VF of CH1

through CH5

CH0 Short-Circuit

Upper OTP triggered

but VIN0 < VSC

CH0 goes off until chip cooled and

then comes back on with current

reduced to 76%. Further OTP triggers

result in reduction to 53%, then 30%.

Thermal event reported in

Fault/Status Register.

Same as CH0

Highest VF of CH1

through CH5

CH0 Short-Circuit

Upper OTP not

triggered but VIIN0

> VSC

CH0 doubled after 6ms time-out.

Time-out reduced to 420µs if above

lower OTP limit

CH1 through CH5 Normal

Highest VF of CH1

through CH5

CH0 Open Circuit with

infinite resistance

Upper OTP not

triggered and VIIN0

< VSC

VOUT will ramp to OVP. CH0 will time-

out after 6ms (800µs if above lower

OTP limit) and switch off. VOUT will

drop to normal level.

CH1 through CH5 Normal

Highest VF of CH1

through CH5

5CH0 LED Open Circuit

but has paralleled

Zener

Upper OTP not

triggered and VIIN0

< VSC

CH0 remains ON and has highest VF,

thus VOUT increases

CH1 through CH5 ON, Q1 through Q5

burn power

VF of CH0

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