ISL97635A

FN6564 Rev.3.00

Page 6 of 29

Sep 26, 2017

Line Regulation

0.1

%

Boost Maximum Duty Cycle

82

%

Boost Minimum Duty Cycle

7%

LX Frequency

1.0

1.2

1.3

MHz

LX Frequency

550

600

650

kHz

LX Leakage Current

ILX_leakage

VLX = 36V, EN = 0

10

µA

REFERENCE

Channel-to-Channel Current Matching

-3.5

±1

+3.5

%

Current Accuracy

±3

%

FAULT DETECTION

Short-Circuit Threshold

Reg0x08 = 0x0F or 0x0B Reg0x00 = 0xFF

7.8

8

8.8

V

Reg0x08 = 0x0E or 0x0A Reg0x00 = 0xFF

2.8

3.1

3.8

V

Over-Temperature Threshold Accuracy

5°

C

Overvoltage Limit on OVP Pin

1.17

1.2

1.23

V

OVP Hysteresis

20

mV

OVP Short Detection Fault Level

300

mV

SMBus INTERFACE

Guaranteed Range for Data, Clock Input Low Voltage

0.8

V

Guaranteed Range for Data, Clock Input High

Voltage

2.1

VDD

V

SMBus Data Line Logic Low Voltage with 1.1kΩ



Series Resistor from Data Bus to SMBDAT pin

0.4

V

SMBus Data Line Logic Low Voltage without Series



Resistor from Data Bus to SMBDAT Pin

0.17

V

Input Leakage on SMBData/SMBClk

-1

1

µA

Nominal Bus Voltage

3V to 5V ±10%

2.7

5.5

V

SMBus TIMING SPECIFICATIONS (Note 4)

SMBus Clock Frequency

10

100

kHz

Bus Free Time between STOP and START Condition

4.7

µs

Hold Time after (Repeated) START Condition. After

this Period, the First Clock is Generated.

4.0

µs

Repeated Start Condition Setup Time

4.7

µs

Stop Condition Setup Time

4.0

µs

Data Hold Time

300



Data Setup Time

250

ns

Clock Low Period

4.7

µs

Clock High Period

4.0

50

µs

Clock/Data Fall Time

300

ns

Clock/Data Rise Time

1000

ns

otherwise noted. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by

characterization and are not production tested. (Continued)

PARAMETER

SYMBOL

CONDITION

MIN

TYP

MAX UNIT